PUBLICATIONS

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    BOOKS  EDITED
    1. Active Matrix Liquid Crystal Displays: Technology and Applications, T. Voutsas, and T.-J. King, Editors, Proceedings of SPIE -- the International Society for Optical Engineering, Vol. 3014 (SPIE: Bellingham, WA, USA), ISBN 0-8194-2425-0, 1997.
    2. CMOS Front-End Materials and Process Technology, T.-J. King, B. Yu, R. J. P. Lander, and S. Saito, Editors, Materials Research Society Symposium Proceedings Vol. 765 (Materials Research Society: Warrendale, PA, USA), 2003.
    3. Materials and Processes for Nonvolatile Memories, A. Claverie, D. Tsoukalas, T-J. King,  and J. Slaughter, Editors, Materials Research Society Symposium Proceedings Vol. 830 (Materials Research Society: Warrendale, PA, USA), 2005.
BOOK CHAPTERS
    1. J. Bokor, T.-J. King, J. Hergenrother, J. Bude, D. Muller, T. Skotnicki, S. Monfray, and G. Timp, “Advanced MOS-Devices,” High Dielectric Constant Materials, Springer Series in Advanced Microelectronics Vol. 16, pp. 667-705, 2005.
    2. T.-J. K. Liu and L. Chang, "Transistor Scaling to the Limit," Moore's Law: Beyond Planar Silicon CMOS and into the Nano Era, Springer-Verlag, 2008.

 

    MAGAZINE ARTICLES
    1. T.-J. King, "Poly-Si TFT technologies for future flat-panel displays," Information Display, Vol. 17, No. 4, pp. 24-26, 2001.
    2. A. E. Franke, T.-J. King, and R. T. Howe, "Integrated MEMS technologies," MRS Bulletin, Vol. 26, No. 4, pp. 291-295, 2001.
    3.  L. Chang, Y.-K. Choi, J. Kedzierski, N. Lindert, P. Xuan, J. Bokor, C. Hu, and T.-J. King, "Moore's Law lives on: ultra-thin body SOI and FinFET CMOS transistors look to continue Moore's Law for many years to come," IEEE Circuits & Devices, Vol. 19, No. 1, pp. 35-42, 2003.
    4. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, and F. Boeuf, "The end of CMOS scaling," IEEE Circuits & Devices, Vol. 21, pp. 16-26, 2005.
    5. T.-J. King, "Challenges and opportunities for nanoscale CMOS technology," The Electrochemical Society INTERFACE, Vol. 14, No. 1, pp. 38-42, 2005.
    6. T.-J. K. Liu, E. Alon, V. Stojanovic, and D. Markovic, "The relay reborn," IEEE Spectrum, April 2012.

 

    REFEREED JOURNAL PUBLICATIONS
    Regular Papers:
    1. T.-J. King, M. G. Hack, and I-W. Wu, "Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors," Journal of Applied Physics, Vol. 75, No. 2, pp. 908-913, 1994.
    2. T.-J. King, J. P. McVittie, K. C. Saraswat, and J. R. Pfiester, "Electrical properties of heavily doped polycrystalline silicon-germanium films," IEEE Transactions on Electron Devices, Vol. 41, No. 2, pp. 228-232, 1994.
    3. T.-J. King and K. C. Saraswat, "Deposition and properties of low-pressure chemical-vapor deposited polycrystalline silicon-germanium films," Journal of the Electrochemical Society, Vol. 141, No. 8, pp. 2235-2241, 1994.
    4. T.-J. King and K. C. Saraswat, "Polycrystalline silicon-germanium thin-film transistors," IEEE Transactions on Electron Devices, Vol. 41, No. 9, pp. 1581-1591, 1994.
    5. J. D. Bernstein, S. Qin, C. Chan, and T.-J. King, "High dose-rate hydrogen passivation of polycrystalline silicon CMOS TFT's by plasma ion implantation," IEEE Transactions on Electron Devices, Vol. 43, No. 11, pp. 1876-1882, 1996.
    6. E. C. Onyiriuka, C. B. Moore, F. P. Fehlner, N. J. Binkowski, D. Salamida, T.-J. King, and J. G. Couillard, "Effect of RCA cleaning on the surface chemistry of glass and polysilicon films as studied by ToF-SIMS and XPS," Surface and Interface Analysis, Vol. 26, pp. 270-277, 1998.
    7. B. Yu, D.-H. Ju, W.-C. Lee, N. Kepler, T.-J. King, and C. Hu, "Gate engineering for deep-submicron CMOS transistors," IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp. 1253-1262, 1998.
    8. S. Qin, Y. Zhou, T. Nakatsugawa, I. F. Husein, C. Chan, and T.-J. King, "Plasma ion implantation hydrogenation of poly-Si CMOS thin-film transistors at low energy and high dose rate using an inductively-coupled plasma source," IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp. 1324-1328, 1998.
    9. S. Yamamichi, A. Yamamichi, D. Park, T.-J. King, and C. Hu, "Impact of time dependent dielectric breakdown and stress induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO3 thin film capacitors for Gbit-scale DRAMs," IEEE Transactions on Electron Devices, Vol. 46, No. 2, pp. 342-347, 1999.
    10. K. L Scott, T.-J. King, K.-N. Leung, and M. A. Lieberman, "Pattern generators and microcolumns for ion beam lithography," Journal of Vacuum Science and Technology B, Vol. 18, No. 6, pp. 3172-3176, 2000.
    11. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET -- a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2320-2325, 2000.
    12. I. Polishchuk, Q. Lu, Y.-C. Yeo, T.-J. King, and C. Hu, "Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET," IEEE Transactions on Device and Materials Reliability, Vol. 1, No. 1, pp. 4-8, 2001.
    13. Y.-C. King, T.-J. King, and C. Hu, "Charge-trap memory device fabricated by oxidation of Si1-xGex," IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 696-700, 2001.
    14. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub-50 nm p-channel FinFET," IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 880-886, 2001.
    15. K. Asano, Y.-K. Choi, T.-J. King, and C. Hu, "Patterning sub-30-nm MOSFET gate with i-line lithography," IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 1004-1006, 2001.
    16. Y.-C. King, C. Kuo, T.-J. King, and C. Hu, "Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation," IEEE Transactions on Electron Devices, Vol. 48, No. 6, pp. 1279-1281, 2001.
    17. I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King, and C. Hu, "Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics," IEEE Transactions on Device and Materials Reliability, Vol. 1, No. 3, pp. 158-162, 2001.
    18. K. L Scott, T.-J. King, K.-N. Leung, and R. F. Pease, "Characterization of multicusp-plasma ion source brightness using micron-scale apertures," Journal of Vacuum Science and Technology B, Vol. 19, No. 6, pp. 2602-2606, 2001.
    19. J. Reijonen, Q. Ji, T.-J. King, K.N. Leung, A. Persaud, and S. Wilde, "Compact focusing system for ion and elecron beams," Journal of Vacuum Science & Technology B, Vol. 20, No. 1, pp. 180-184, 2002.
    20. 2002 EDS Paul Rappaport Award: Y.-C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C. Hu, "Design and fabrication of 50-nm thin-body p-MOSFETS with a SiGe heterostructure channel," IEEE Transactions on Electron Devices, Vol. 49, No. 2, pp. 279-286, 2002.
    21. Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp. 436-441, 2002.
    22. P. Ranade, H. Takeuchi, W.-C. Lee, V. Subramanian, and T.-J. King, "Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs," IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1436-1443, 2002.
    23. Q. Ji, X. Jiang, T.-J. King, K.-N. Leung, K. Standiford, and S. B. Wilde, "Improvement in brightness of multicusp-plasma ion source," Journal of Vacuum Science & Technology B, Vol. 20, No. 6, pp. 2717-2720, November 2002.
    24. H. Takeuchi, P. Ranade, and T.-J. King, "Suppression of boron TED by low temperature SPC anneal prior to dopant activation," IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2343 -2344, 2002.
    25. K. J. Yang, T.-J. King, C. Hu, S. Levy, and H. N. Al-Shareef, "Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics," Solid-State Electronics, Vol. 47, pp. 149-153, 2003.
    26. Y.-C. Jeon, A. Franke, T.-J. King, and R. T. Howe, "Properties of phosphorus-doped poly-SiGe films for MEMS applications, " Journal of The Electrochemical Society, Vol. 150, No. 1, pp. H1-H6, 2003.
    27. L. Chang, K. J. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu, "Direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs," IEEE Transactions on Electron Devices, Vol. 49, No. 12, pp. 2288-2295, 2002.
    28. A. E. Franke, J. M. Heck, T.-J. King, and R. T. Howe, "Polycrystalline silicon-germanium films for integrated microsystems," Journal of Microelectromechanical Systems, Vol. 12, pp. 160-171, 2002.
    29. Y. Cao, R. A. Groves, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, X. Huang, T.-J. King, and C. Hu, "Frequency-independent equivalent-circuit model for on-chip spiral inductors," IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, pp. 419-426, 2003.
    30. X. Huang, P. Restle, T. Bucelot, Y. Cao, T.-J. King, and C. Hu, "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, pp. 457-463, 2003.
    31. D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King, and C. Hu, "Molybdenum gate work function engineering for ultra-thin-body silicon-on-insulator (UTB SOI) MOSFETs," Japanese Journal of Applied Physics Part 1, Vol. 42, No. 4B, pp. 1979-1982, 2003.
    32. M. She and T.-J. King, "Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance," IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp. 1934-1940, 2003.
    33. Invited: L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, "Extremely scaled silicon nano-CMOS devices," Proceedings of the IEEE, Vol. 91, No. 11, pp. 1860-1873, 2003.
    34. C. Kuo, T.-J. King, and C. Hu, "A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications," IEEE Transactions on Electron Devices, Vol. 50, No. 12, pp. 2408-2416, 2003.
    35. H. Takeuchi and T.-J. King, "SCA (Surface Charge Analysis) of ultrathin HfO2, SiO2, and Si3N4," Journal of the Electrochemical Society, Vol. 151, No. 2, pp. H44-H48, 2004.
    36. H. Takeuchi, P. Ranade, and T.-J. King, "Low temperature dopant activation technology using elevated Ge-S/D structure," Applied Surface Science, Vol. 224, Issues 1-4, pp. 73-76, 2004.
    37. M.-A. E. Eyoum and T.-J. King, "Low resistance silicon-germanium technology for modular integration of MEMS with electronics," Journal of the Electrochemical Society, Vol. 151, No. 3, pp. J21-J25, 2004.
    38. H. Takeuchi and T.-J. King, "Spectroscopic ellipsometry study on the oxidation of pure hafnium on silicon," Journal of Vacuum Science and Technology A, July/August 2004.
    39. S. Sedky, R. T. Howe, and T.-J. King, "Pulsed-laser annealing, a low-thermal-budget technique for eliminating stress gradient in poly-SiGe MEMS structures," Journal of Microelectromechanical Systems, Vol. 13, No. 4, 2004.
    40. S. Sedky, J. Schroeder, T. Sands, T.-J. King, and R. T. Howe, "Effect of excimer laser annealing on the structural properties of silicon germanium films," Journal of Materials Research, Vol. 19, No. 12, pp. 3503-3511, 2004.
    41. D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King, "Molybdenum gate technology for ultra-thin-body MOSFETs and FinFETs," IEEE Transactions on Electron Devices, Vol. 51, No. 12, pp. 1989-1996, 2004.
    42. Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, "Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 1, pp. 158-162, 2005.
    43. S. Xiong, T.-J. King, and J. Bokor, "Study of the extrinsic parasitics in nano-scale transistors," Semiconductor Science and Technology, Vol. 20, pp. 652-657, 2005.
    44. S. Xiong, T.-J. King, and J. Bokor, "A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain," IEEE Transactions on Electron Devices, Vol. 52, No. 8, pp. 1859-1867, 2005.
    45. H. Takeuchi, M. She, K. Watanabe, and T.-J. King, "Damage-less sputter deposition by plasma charge trap for metal gate technologies," IEEE Transactions on Semiconductor Manufacturing, Vol. 18, No. 3, pp. 350-354, 2005.
    46. H. Takeuchi, A. Wung, X. Sun, R. T. Howe, and T.-J. King, "Thermal budget limits of quarter-micron foundry CMOS for post-processing MEMS devices," IEEE Transactions on Electron Devices, Vol. 52, No. 9, pp. 2081-2086, 2005.
    47. Q. Ji, K.-N. Leung, T.-J. King, X. Jiang, and B. R. Appleton, "Development of focused ion beam systems with various ion species," Nuclear Instruments and Methods in Physics Research B, Vol. 241, pp. 335-340, 2005.
    48. L. Xu, C. Grigoropoulos, and T.-J. King, "High-performance thin-silicon-film transistors fabricated by double laser crystallization," Journal of Applied Physics, Vol. 99, pp. 0345408-1 to 0345408-6, 2006.
    49. C. W. Low, T.-J. K. Liu, and R. T. Howe, "Characterization of polycrystalline silicon-germanium film deposition for modularly integrated MEMS applications," IEEE Journal of Microelectromechanical Systems, Vol. 16, No. 1, pp. 68-77, 2007.
    50. R. A. Vega and T.-J. K. Liu, "Low pressure chemical vapor deposition of in-situ-doped n- and p-type Si1-xGex films at 425oC, Journal of the Electrochemical Society, Vol. 154, No. 9, pp. H789-H793, 2007.
    51. Y. Yasuda, T.-J. K. Liu, and C. Hu, "Flicker-noise impact on scaling of mixed-signal CMOS with HfSiON," IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 417-422, 2008.
    52. Invited: G. K. Fedder, R. T. Howe, T.-J. K. Liu, and E. P. Quevy, "Technologies for co-fabricating MEMS and electronics," Proceedings of the IEEE, Vol. 96, No. 2, pp. 306-322, 2008.
    53. G. Liu, P. Haldi, T.-J. K. Liu, and A. M. Niknejad, "Fully integrated CMOS power amplifier with efficiency enhancement at power back-off," IEEE Journal of Solid-State Circuits, Vol. 43, No. 3, pp. 600-609, 2008.
    54. A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, C. Hu, and T.-J. K. Liu, "Forward body biasing as a bulk-Si CMOS technology scaling strategy," IEEE Transactions on Electron Devices, Vol. 55, No. 10, pp. 2657-2664, 2008.
    55. R. A. Vega and T.-J. K. Liu, "A comparative study of dopant-segregated Schottky and raised source/drain double-gate MOSFETs," IEEE Transactions on Electron Devices, Vol. 55, No. 10, pp. 2665-2677, 2008.
    56. W. Y. Choi, T. Osabe and T.-J. K. Liu, "Nano-electro-mechanical nonvolatile memory (NEMory) cell design and scaling," IEEE Transactions on Electron Devices, Vol. 55, No. 12, pp. 3482-3488, 2008.
    57. A. Carlson and T.-J. K. Liu, "Low variability negative and iterative spacer processes for sub-30nm lines and holes," Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), Vol. 8, 011009, 2009.
    58. V. Varadarajan and T.-J. K. Liu, "FinFET design for tolerance to statistical dopant fluctuations," IEEE Transactions on Nanotechnology, Vol. 8, No. 3, pp. 375-378, 2009.
    59. R. A. Vega and T.-J. K. Liu, "Three-dimensional FinFET source/drain and contact design optimization study," IEEE Transactions on Electron Devices, Vol. 56, No. 7, pp. 1483-1492, 2009.
    60. R. A. Vega and T.-J. K. Liu, "Dopant-segregated Schottky source/drain double-gate MOSFET design in the direct source-to-drain tunneling regime," IEEE Transactions on Electron Devices, Vol. 56, No. 9, pp. 2016-2026, 2009.
    61. Z. Guo, A. Carlson, L.-T. Pan, K. Duong, T.-J. K. Liu, and B. Nikolic, "Large-scale SRAM variability characterization in 45nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, pp. 3174-3192, 2009
    62. K. Patel, T.-J. K. Liu, C. J. Spanos, "Gate line edge roughness model for estimation of FinFET performance variability," IEEE Transactions on Electron Devices, Vol. 56, No. 12, pp. 3055-3063, 2009.
    63. H. Kam and T.-J. K. Liu, "Pull-in and release voltage design for nanoelectromechanical field-effect transistors," IEEE Transactions on Electron Devices, Vol. 56, No. 12, pp. 3072-3082, 2009.
    64. R. A. Vega, V. C. Lee and T.-J. K. Liu, "The effect of random dopant fluctuation on specific contact resistivity," IEEE Transactions on Electron Devices, Vol. 57, No. 1, pp. 273-281, 2010.
    65. D. Lee, H. Tran, and T.-J. K. Liu, "Characterization of nanometer-scale gap formation," Journal of the Electrochemical Society, Vol. 157, No. 1, pp. H94-H98, 2010.
    66. X. Sun and T.-J. K. Liu, "Spacer gate lithography for reduced variability due to line edge roughness," IEEE Transactions on Semiconductor Manufacturing, Vol. 23, No. 2, pp. 311-315, 2010.
    67. R. A. Vega and T.-J. K. Liu, "Dopant-segregated Schottky junction tuning with flurorine pre-silicidation ion implant," IEEE Transactions on Electron Devices, Vol. 57, No. 5, pp. 1084-1092, 2010.
    68. A. Carlson, Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. K. Liu, and B. Nikolic, "SRAM read/write margin enhancements using FinFETs," IEEE Transactions on VLSI Systems, Vol. 18, No. 6, pp. 887-900, 2010.
    69. Invited: T.-J. K. Liu and H. Kam, "Mechanical computing redux: relays for integrated circuit applications," Hitachi Research Institute periodical, Vol. 5-1, pp. 38-42, 2010.
    70. C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, C. Mazure, B. Nikolic, and T.-J. K. Liu, "Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node," IEEE Transactions on Electron Devices, Vol. 57, No. 6, pp. 1301-1309, 2010.
    71. S.-H. Kim, Z. A. Jacobson and T.-J. K. Liu, "Impact of body doping and thickness on the performance of germanium-source TFETs," IEEE Transactions on Electron Devices, Vol. 57, No. 7, pp. 1710-1713, 2010.
    72. S. Lee, Y. W. Jeon, T.-J. K. Liu, D. H. Kim, and D. M. Kim, "A novel self-aligned 4-bit SONOS-type non-volatile memory cell with T-gate and I-shaped FinFET structure," IEEE Transactions on Electron Devices, Vol. 57, No. 8, pp. 1728-1736, 2010.
    73. D. Lee, H. Tran, B. Ho, and T.-J. K. Liu, "Dlectrical characterization of etch rate for micro- and nano-scale gap formation," IEEE/ASME Journal of Microelectromechanical Systems, Vol. 19, No. 5, pp. 1260-1263, 2010.
    74. I. Laboriante, B. Bush, D. Lee, F. Liu, T.-J. K. Liu, C. Carraro, and R. Maboudian, "Interfacial adhesion between rough surfaces of polycrystalline silicon and its implications for M/NEMS technology," Journal of Adhesion Science and Technology, Vol. 24, No. 15-16, pp. 2545-2556, 2010.
    75. Invited: V. Pott, H. Kam, R. Nathaniel, J. Jeon, E. Alon, and T.-J. K. Liu, "Mechanical computing redux: Relays for integrated circuit applications," Proceedings of the IEEE, Vol. 98, No. 12, pp. 2076-2094, 2010.
    76. R. A. Vega and T.-J. K. Liu, "Comparative study of FinFET vs. quasi-planar HTI MOSFET for ultimate scalability," IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3250-3256, 2010.
    77. H. Kam, T.-J. K. Liu, V. Stojanovic, D. Markovic, and E. Alon, "Design, optimization and scaling of MEM relays for ultra-low-power digital logic," IEEE Transactions on Electron Devices, Vol. 58, No. 1, pp. 236-250, 2011.
    78. Invited: M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.-J. K. Liu, D. Markovic, E. Alon, and V. Stojanovic, "Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications," IEEE Journal of Solid-State Circuits, Vol. 46, No. 1, pp. 308-320, 2011.
    79. C. Shin, N. Damrongplasit, X. Sun, Y. Tsukamoto, B. Nikolic and T.-J. K. Liu, "Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22 nm node," IEEE Transactions on Electron Devices, Vol. 58, No. 7, pp. 1846-1854, 2011.
    80. B. Ho, N. Xu, and T.-J. K. Liu, "Study of high-performance Ge pMOSFET scaling accounting for direct source-to-drain tunneling," IEEE Transactions on Electron Devices, Vol. 58, No. 9, pp. 2895-2902, 2011.
    81. N. Xu, L. T.-H. Wang, A. Neureuther, and T.-J. K. Liu, "Physically based modeling of stress-induced variation in nano-scale transistor performance," IEEE Transactions on Electron Devices, Vol. 11, No. 3, pp. 378-386, 2011.
    82. X. Sun, V. Moroz, N. Damrongplasit, C. Shin, and T.-J. K. Liu, "Variation study of the planar ground-plane bulk MOSFET, SOI FinFET and tri-gate bulk MOSFET designs," IEEE Transactions on Electron Devices, Vol. 58, No. 10, pp. 3294-3299, 2011.
    83. N. Damrongplasit, C. Shin, S. H. Kim, R. A. Vega, and T.-J. K. Liu, "Study of random dopant fluctuation effects in germanium-source tunnel FETs," IEEE Transactions on Electron Devices, Vol. 58, No. 10, pp. 3541-3548, 2011.
    84. W.-Y. Loh, K. Jeon, C. Y. Kang, J. Oh, T.-J. K. Liu, H.-H. Tseng, W. Xiong, P. Majhi, R. Jammy and C. Hu, "Highly scaled (Lg ~ 56 nm) gate-last Si tunnel field effect transistors with ION > 100 mA/mm," Solid State Electronics, Vol. 65-66, pp. 22-27, 2011.
    85. C. Shin, C. H. Tsai, M. H. Wu, C. F. Chang, Y. R. Liu, C. Y. Kao, G. S. Lin, K. L Chiu, C.-S. Fu, T.-t. Tsai, C. W. Liang, B. Nikolic, and T.-J. K. Liu, "Quasi-planar bulk CMOS technology for improved SRAM scalability," Solid State Electronics, Vol. 65-66, pp. 184-190, 2011.
    86. S. O. Toh, Z. Guo, T.-J. K. Liu, and B. Nikolic, "Characterization of dynamic SRAM stability in 45 nm CMOS," IEEE Journal of Solid State Circuits, Vol. 46, No. 11, pp. 2702-2712, 2011.
    87. H. Kam, E. Alon, and T.-J. K. Liu, "Design requirements for steeply switching logic devices," IEEE Transactions on Electron Devices, Vol. 59, No. 2, pp. 326-334, 2012.
    88. M. H. Cho, C. Shin, and T.-J. K. Liu, "Design optimization of back-gated thin-body silicon-on-insulator capacitorless dynamic random access memory cell," Japaness Journal of Applied Physics, Vol. 51, No. 2, pp. 02BD02-02BD02-6, 2012.
    89. B. Ho, N. Xu, and T.-J. K. Liu, "pMOSFET performance enhancement with strained-Si1-xGex channels," IEEE Transactions on Electron Devices, Vol. 59, No. 5, pp. 1468-1474, 2012.
    90. N. Xu, B. Ho, M. Choi, V. Moroz, and T.-J. K. Liu, "Effectiveness of stressors in aggressively scaled FinFETs," IEEE Transactions on Electron Devices, Vol. 59, No. 6, pp. 1592-1598, 2012.
    91. P. Matheu, B. Ho, Z. Jacobson, and T.-J. K. Liu, "Planar GeOI TFET performance improvement with back biasing," IEEE Transactions on Electron Devices, Vol. 59, No. 6, pp. 1629-1635, 2012.
    92. B. Ho, X. Sun, N. Xu, T. Sako, K. Maekawa, M. Tomoyasu, Y. Akasaka, O. Bonnin, B.-Y. Nguyen, and T.-J. K. Liu, "First demonstration of quasi-planar segmented-channel MOSFET design for improved scalability," IEEE Transactions on Electron Devices, Vol. 59, No. 8, pp. 2273-2276, 2012.
    93. B. Ho, X. Sun, C. Shin, and T.-J. K. Liu, "Design optimization of multigate bulk MOSFETsIEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 28-33, 2013.
    94. B. Ho, N. Xu, B. Wood, V. Tran, S. Chopra, Y. Kim, B.-Y. Nguyen, O. Bonnin, C. Mazure, S. Kuppurao, C.-P. Chang, and T.-J. K. Liu, "Fabrication of Si1-xGex/Si pMOSFETs using corrugated substrates for improved ION and reduced layout-width dependence," IEEE Transactions on Electron Devices, Vol. 60, No. 1, pp. 153-158, 2013.
    95. D. Chen, Z. Jacobson and T.-J. K. Liu, "Raised-source/drain double-gate transistor design optimization for low operating power," IEEE Transactions on Electron Devices, Vol. 60, No. 3, pp. 1040-1045, 2013.
    96. J. Yaung, L. Hutin, J.Jeon and T.-J. K. Liu, "Adhesive force characterization for MEM logic relays with sub-micron contacting regions," IEEE/ASME Journal of Microelectromechanical Systems, Vol. 22, 2013.
    97. N. Damrongplasit, S. H. Kim, C. Shin and T.-J. K. Liu, "Impact of gate line-edge roughness (LER) vs. random dopant fluctuations (RDF) on Germanium-source tunnel FET performance," IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp. 1061-1067, 2013.
    98. J. Yaung, L. Hutin, J. Jeon and T.-J. K. Liu, “Adhesive force characterization for MEM logic relays with sub-micron contacting regions,” IEEE/ASME Journal of Microelectromechanical Systems, Vol. 23, No. 1, pp. 198-203, 2014.
    99. R. Going, J. Loo, T.-J. K. Liu and M. C. Wu, “Germanium gate photoMOSFET integrated to silicon photonics,” IEEE Journal of Selected Topics in Quantum Electronics, Vol. 20, No. 4, 2014.
    100. L. Hutin, W. Kwon, C. Qian and T.-J. K. Liu, “Electromechanical diode cell scaling for high-density nonvolatile memory,” IEEE Transactions on Electron Devices, Vol. 61, No. 5, pp. 1382-1387, 2014.
    101. Y.-B. Liao, M.-H. Chiang, N. Damrongplasit, W.-C. Hsu and T.-J. K. Liu, “Design of gate-all-around silicon MOSFETs for 6-T SRAM area efficiency and yield,” IEEE Transactions on Electron Devices, Vol. 61, No. 7, pp. 2371-2377, 2014.

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    Letters and Briefs:
    1. T.-J. King, J. R. Pfiester, and K. C. Saraswat, "A variable-work-function polycrystalline-Si1-xGex gate material for submicrometer CMOS technologies," IEEE Electron Device Letters, Vol. 12, No. 10, pp. 533-535, 1991.
    2. T.-J. King, K. C. Saraswat, and J. R. Pfiester, "PMOS transistors in LPCVD polycrystalline silicon-germanium films," IEEE Electron Device Letters, Vol. 12, No. 11, pp. 584-586, 1991.
    3. T.-J. King, and K. C. Saraswat, "Low-temperature (<550oC) fabrication of poly-Si thin-film transistors," IEEE Electron Device Letters, Vol. 13, No. 6, pp. 309-311, 1992.
    4. M. Cao, T.-J. King, and K. C. Saraswat, "Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films," Applied Physics Letters, Vol. 61, No. 6, pp. 672-674, 1992.
    5. S. Jurichich, T.-J. King, K. C. Saraswat, and J. Mehlhaff, "Low thermal budget polycrystalline silicon-germanium thin-film transistors fabricated by rapid thermal annealing," Japanese Journal of Applied Physics, Vol. 33, No. 8, pp. L1139-L1141, 1994.
    6. D. S. Bang, M. Cao, A. Wang, K. C. Saraswat, and T.-J. King, "Resistivity of boron and phosphorus doped polycrystalline Si1-xGex films," Applied Physics Letters, Vol. 66, No. 2, pp. 195-197, 1995.
    7. J. D. Bernstein, S. Qin, C. Chan, and T.-J. King, "Hydrogenation of polycrystalline silicon thin film transistors by plasma ion implantation," IEEE Electron Device Letters, Vol. 16, No. 10, pp. 421-423, 1995.
    8. B. Yu, D.-H. Ju, N. Kepler, T.-J. King, and C. Hu, "Impact of Gate Microstructure on Complementary Metal-Oxide-Semiconductor Transistor Performance," Japanese Journal of Applied Physics Part 2, Letters, Vol. 36, No. 9AB, pp. L1150-L1152, 1997.
    9. W.-C. Lee, Y.-C. King, T.-J. King, and C. Hu, "Observation of reduced poly-gate depletion effect for poly-Si0.8Ge0.2-gate NMOS devices," Electrochemical and Solid State Letters, Vol. 1, No. 1, pp. 58-59, 1998.
    10. W.-C. Lee, Y.-C. King, T.-J. King, and C. Hu, "Investigation of poly-Si1-xGex for dual gate CMOS technology," IEEE Electron Device Letters, Vol. 19, No. 7, pp. 247-249, 1998.
    11. Q. Lu, D. Park, A. Kalnitsky, C. Chang, C.-C. Cheng, S. P. Tay, T.-J. King, and C. Hu, "Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics," IEEE Electron Device Letters, Vol. 19, No. 9, pp. 341-342, 1998.
    12. D. Park, Y.-C. King, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay, and C.-C. Cheng, "Transistor characteristics with Ta2O5 gate dielectric," IEEE Electron Device Letters, Vol. 19, No. 11, pp. 441-443, 1998.
    13. W.-C. Lee, T.-J. King, and C. Hu, "Observation of reduced boron penetration and poly-gate depletion for poly-Si0.8Ge0.2-gated PMOS devices," IEEE Electron Device Letters, Vol. 20, No. 1, pp. 9-11, 1999.
    14. W.-C. Lee, B. Watson, T.-J. King, and C. Hu, "Enhancement of PMOS device performance with poly-SiGe Gate," IEEE Electron Device Letters, Vol. 20, No. 5, pp. 232-234, 1999.
    15. W.-C. Lee, T.-J. King, and C. Hu, "Evidence of direct hole tunneling through ultrathin gate oxide using P+ poly-SiGe gate," IEEE Electron Device Letters, Vol. 20, No. 6, pp. 268-270, 1999.
    16. Y.-J. Tung, J. Boyce, J. Ho, X. Huang, and T.-J. King, "A comparison of hydrogen and deuterium plasma treatment effects on polysilicon TFT performance and DC reliability," IEEE Electron Device Letters, Vol. 20, No. 8, pp. 387-389, 1999.
    17. Y.-C. King, T.-J. King, and C. Hu, "A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide," IEEE Electron Device Letters, Vol. 20, No. 8, pp. 409-411, 1999.
    18. Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C. Hu, "Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel," IEEE Electron Device Letters, Vol. 21, No. 4, pp. 161-163, 2000.
    19. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Letters, Vol. 21, No. 5, pp. 254-255, 2000.
    20. Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T.P. Ma, "Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric," IEEE Electron Device Letters, Vol. 21, No. 11, pp. 540-542, 2000.
    21. Y. C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, and D.-L. Kwong, "Dual metal gate CMOS technology with ultrathin silicon nitride gate dielectric," IEEE Electron Device Letters, Vol. 22, No. 5, pp. 227-229, 2001.
    22. Q. Lu, Y. C. Yeo, K. J. Yang, R. Lin, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, X. Guo, Z. Luo, X. Wang, and T.-P. Ma, "Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric," IEEE Electron Device Letters, Vol. 22, No. 7, pp. 324-326, 2001.
    23. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, "Dual work function metal gate CMOS technology using metal interdiffusion," IEEE Electron Device Letters, Vol. 22, No. 9, pp. 444-446, 2001.
    24. Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, "Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain," IEEE Electron Device Letters, Vol. 22, No. 9, pp. 447-448, 2001.
    25. N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, "Sub-60-nm quasi-planar FinFETs fabricated using a simplified process," IEEE Electron Device Letters, Vol. 22, No. 10, pp. 487-489, 2001.
    26. P. Ranade, H. Takeuchi, T.-J. King, and C. Hu, "Work function engineering of molybdenum gate electrodes by nitrogen implantation," Electrochemical and Solid-State Letters, Vol. 4, No. 11, pp. G85-G87, 2001.
    27. Y.-K. Choi, T.-J. King, and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Electron Device Letters, Vol. 23, No. 1, pp. 25-27, 2002.
    28. P. Ranade, H. Takeuchi, V. Subramanian, and T.-J. King, "Observation of Boron and Arsenic mediated interdiffusion across Germanium/Silicon interfaces," Electrochemical and Solid-State Letters, Vol. 5, No. 2, pp. G5-G7, 2002.
    29. R. Lin, Q. Lu, P. Ranade, T.-J. King, and C. Hu, "An adjustable work function technology using Mo gate for CMOS devices," IEEE Electron Device Letters, Vol. 23, No. 1, pp. 49-51, 2002.
    30. M. She, T.-J. King, C. Hu, W. Zhu, Z. Luo, J.-P. Han, and T.-P. Ma, "JVD silicon nitride as tunnel dielectric in p-channel flash memory," IEEE Electron Device Letters, Vol. 23, No. 2, pp. 91-93, 2002.
    31. I. Polishchuk P. Ranade, T.-J. King, and C. Hu, "Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion," IEEE Electron Device Letters, Vol. 23, No. 4, pp. 200-202, 2002.
    32. P. Ranade, H. Takeuchi, V. Subramanian, and T.-J. King, "A novel elevated source/drain PMOSFET formed by Ge-B/Si intermixing," IEEE Electron Device Letters, Vol. 23, No. 4, pp. 218-220, 2002.
    33. H. Takeuchi, P. Ranade, V. Subramanian, and T.-J. King, "Observation of dopant-mediated intermixing at Ge/Si interface," Applied Physics Letters, Vol. 80, No. 20, pp. 3706-3708, May 2002.
    34. Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, "Effects of high-k gate dielectric materials on metal and silicon gate workfunctions," IEEE Electron Device Letters, Vol. 23, No. 6, pp. 342-344, 2002.
    35. C. Kuo, T.-J. King, and C. Hu, "A capacitorless double-gate DRAM cell," IEEE Electron Device Letters, Vol. 23, No. 6, pp. 345-347, 2002.
    36. J.-S. Lee, Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, "Low-frequency noise characteristics in p-channel FinFETs," IEEE Electron Device Letters, Vol. 23, No. 12, pp. 722-724, 2002.
    37. H. Takeuchi and T.-J. King, "Suppression of boron TED by low temperature SPC anneal prior to dopant activation," IEEE Transactions on Electron Devices, Vol. 29, No. 12, pp. 2343-2344, 2002.
    38. J.-S. Lee, D. Ha, Y.-K. Choi, T.-J. King, and J. Bokor, "Low-frequency noise characteristics of ultrathin body p-MOSFETs with Molybdenum gate, IEEE Electron Device Letters, Vol. 24, No. 1, pp. 31-33, 2003.
    39. J.-S. Lee, Y.-K. Choi, D. Ha, S. Balasubramanian, T.-J. King, and J. Bokor, "Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs, IEEE Electron Device Letters, Vol. 24, No. 3, pp. 186-188, 2003.
    40. M. She, H. Takeuchi, and T.-J. King, "Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory," IEEE Electron Device Letters, Vol. 24, No. 5, pp. 309-311, 2003.
    41. H. Takeuchi and T.-J. King, "Scaling limits of hafnium-silicate films for CMOS gate-dielectric application," Applied Physics Letters, Vol. 83, No. 4, pp. 788-790, July 2003.
    42. C. Kuo, T.-J. King, and C. Hu, "Direct tunneling RAM (DT-RAM) for high-density memory applications," IEEE Electron Device Letters, Vol. 24, No. 7, pp. 475-477, 2003.
    43. C. Kuo, T.-J. King, and C. Hu, Bias polarity dependent effects of P+ floating gate EEPROMs," IEEE Transactions on Electron Devices, Vol. 51, No. 2, pp. 282-285, 2004.
    44. H. Takeuchi, E. Quevy, S. A. Bhave, T.-J. King, and R. T. Howe, "Ge-blade damascene process for post-CMOS integration of nano-mechanical resonators," IEEE Electron Device Letters, Vol. 25, No. 8, pp. 529-531, 2004.
    45. W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith, D. Lewis, C. R. Cleavelin, R. Wise, S. Yu, M. Pas, T.-J. King, and J. P. Colinge, "Improvement of FinFET electrical characteristics by hydrogen annealing," IEEE Electron Device Letters, Vol. 25, No. 8, pp. 541-543, 2004.
    46. H. Y. Wong, H. Takeuchi, T.-J. King, M. Ameen, and A. Agarwal, "Elimination of poly-Si gate depletion for sub-65nm CMOS technologies by excimer laser annealing," to appear in IEEE Electron Device Letters, Vol. 26, No. 4, pp. 234-236, 2005.
    47. A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, T.-J. K. Liu, and C. Hu, "MOSFET design for forward body biasing scheme," IEEE Electron Device Letters, Vol. 27, No. 5, pp. 387-389, 2006.
    48. A. Hokazono, S. Balasubramanian, K. Ishimaru, H. Ishiuchi, C. Hu, and T.-J. K. Liu, "MOSFET hot-carrier reliability improvement by forward body bias," IEEE Electron Device Letters, Vol. 27, No. 7, pp. 605-608, 2006.
    49. W. Xiong, C. R. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, and T.-J. K. Liu, "Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility," IEEE Electron Device Letters, Vol. 27, No. 7, pp. 612-614, 2006.
    50. K. Shin, W. Xiong, C. Y. Cho, C. R. Cleavelin, T. Schulz, K. Schruefer, P. Patruno, L. Smith, and T.-J. K. Liu, "Study of bending-induced strain effects on MuGFET performance," IEEE Electron Device Letters, Vol. 27, No. 8, pp. 671-673, 2006.
    51. Q. Lu and T.-J. K. Liu, "Trap energy levels associated with indium and boron impurities in SiO2," Solid-State and Electrochemical Letters, Vol. 9, No. 9, pp. G296-G298, 2006.
    52. D. Good, P. Wickboldt, and T.-J. K. Liu, "Defect passivation in poly-Si TFTs by ion implantation and pulsed laser annealing," IEEE Electron Device Letters, Vol. 27, No. 10, pp. 840-842, 2006.
    53. A. Padilla, T.-J. K. Liu, J. W. Hyun, I. Yoo, and Y. Park, "Dual-bit gate-sidewall-storage FinFET non-volatile memory cell and new method of charge detection," IEEE Electron Device Letters, Vol. 28, No. 6, pp. 502-505, 2007.
    54. D. Lee, T. Seidel, J. Dalton, and T.-J. K. Liu, "ALD refill of nanometer-scale gaps with high-k dielectric for advanced CMOS technologies," Electrochemical and Solid-State Letters, Vol. 10, No. 9, pp. H257-H259, 2007.
    55. X. Sun, Q. Lu, H. Takeuchi, S. Balasubramanian, and T.-J. K. Liu, "Selective enhancement of SiO2 etch rate by Ar ion implantation for improved etch depth control," Electrochemical and Solid-State Letters, Vol. 10, No. 9, pp. D89-D91, 2007.
    56. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Letters, Vol. 28, No. 8, pp. 743-745, 2007.
    57. J. Lai and T.-J. K. Liu, "Defect passivation by selenium ion implantation for poly-Si thin film transistors," IEEE Electron Device Letters, Vol. 28, No. 8, pp. 725-727, 2007.
    58. F. W. DelRio, J. Lai, N. Ferralis, T.-J. K. Liu, and R. Maboudian, "Al-2%Si induced crystallization of amorphous silicon," Electrochemical and Solid-State Letters, Vol. 10, No. 11, pp. H337-H339, 2007
    59. X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda, C. Shin, and T.-J. K. Liu, "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap," IEEE Electron Device Letters, Vol. 29, no. 5, pp. 491-493, 2008.
    60. R. Nathanael, W. Xiong, and T.-J. K. Liu, "Impact of gate-induced strain on MuGFET reliability," IEEE Electron Device Letters, Vol. 29, pp. 916-919, 2008.
    61. P. Kalra, N. Vora, P. Majhi, P. Y. Hung, H. H. Tseng, R. Jammy, and T.-J. K. Liu, "Modified NiSi/Si Schottky barrier height by nitrogen implantation," Electrochemical and Solid-State Letters, Vol. 12, No. 1, pp. H1-H3, 2009.
    62. W. Y. Choi and T.-J. K. Liu, "Reliability of nanoelectromechanical nonvolatile memory (NEMory) cells," IEEE Electron Device Letters, Vol. 30, No. 3, pp. 269-271, 2009.
    63. D. T. Lee, T. Osabe, and T.-J. K. Liu, "Scaling limitations for flexural beams used in electromechanical devices," IEEE Transactions on Electron Devices, Vol. 56, No. 4, pp. 688-691, 2009.
    64. C. Shin, X. Sun, and T.-J. K. Liu, "Study of random-dopant-fluctuation (RDF) effects for the tri-gate bulk MOSFET," IEEE Transactions on Electron Devices, Vol. 56, No. 7, pp. 1538-1542, 2009.
    65. X. Sun and T.-J. K. Liu, "Scale length assessment of the tri-gate bulk MOSFET design," IEEE Transactions on Electron Devices, Vol. 56, No. 11, pp. 2840-2842, 2009.
    66. R. Vega and T.-J. K. Liu, "Low standby power bulk MOSFET design using high-k trench isolation," IEEE Electron Device Letters, Vol. 30, No. 12, pp. 1380-1382, 2009.
    67. J. Jeon, V. Pott, H. Kam, R. Nathanael, E. Alon, and T.-J. K. Liu, "Perfectly complementary relay design for digital logic applications," IEEE Electron Device Letters, Vol. 31, No. 4, pp. 371-373, 2010.
    68. J. Jeon, R. Nathanael, V. Pott, and T.-J. K. Liu, "Four-terminal relay design for improved body effect," IEEE ELectron Device Letters, Vol. 31, No. 5, pp. 515-517, 2010.
    69. S. H. Kim, Z. A. Jacobson, and T.-J. K. Liu, "Impact of body doping and thickness on the performance of germanium-source TFETs," IEEE Transactions on Electron Devices, Vol. 57, No. 7, pp. 1710-1713, 2010.
    70. J. Jeon, V. Pott, H. Kam, R. Nathanael, E. Alon, and T.-J. K. Liu, "Seesaw relay logic and memory circuits," IEEE/ASME Journal of MicroElectroMechanical Systems, Vol. 19, No. 4, pp. 1012-1014, 2010.
    71. R. Vega and T.-J. K. Liu, "DSS MOSFET with tunable SDE regions by Fluorine pre-silicidation ion implant (F-PSII)," IEEE Electron Device Letters, Vol. 31, No. 8, pp. 785-787, 2010.
    72. R. Nathanael, V. Pott, H. Kam, J. Jeon, E. Alon, and T.-J. K. Liu, "Four-terminal-relay body-biasing schemes for complementary logic circuits," IEEE Electron Device Letters, Vol. 31, No. 8, pp. 890-892, 2010.
    73. S. H. Kim, S. Agarwal, Z. A. Jacobson, P. Matheu, C. Hu, and T.-J. K. Liu, "Tunnel field effect transistor with raised germanium source," IEEE Electron Device Letters, Vol. 31, No. 10, pp. 1107-1109, 2010.
    74. J. Jeon, W. Kwon, and T.-J. K. Liu, "Embedded memory capability of four-terminal relay technology," IEEE Transactions on Electron Devices, Vol. 58, No. 3, pp. 891-894, 2011.
    75. A. Guo, P. Matheu, and T.-J. K. Liu, "SOI TFET Ion/Ioff enhancement via back biasing," IEEE Transactions on Electron Devices, Vol. 58, No. 10, pp. 3283-3285, 2011.
    76. W. Kwon, J. Jeon, L. Hutin, and T.-J. K. Liu, "Electromechanical diode cell for cross-point nonvolatile memory arrays," IEEE Electron Device Letters, Vol. 33, No. 2, pp. 131-133, 2012.
    77. J. Jeon, L. Hutin, R. Jevtic, N. Liu, Y. Chen, R. Nathanael, W. Kwon, M. Spencer, E. Alon, B. Nikolic, and T.-J. K. Liu, "Multi-input relay design for more compact implementation of digital logic circuits," IEEE Electron Device Letters, Vol. 33, No. 2, pp. 281-283, 2012..
    78. M. H. Cho and T.-J. K. Liu, "Variation study and implications for BJT-based thin-body capacitorless DRAM," IEEE Electron Device Letters , Vol. 33, No. 3, pp. 312-314, 2012.
    79. N. Xu, B. Ho, F. Andrieu, L. Smith, B.-Y. Nguyen, O. Weber, T. Poiroux, O. Faynot and T.-J. K. Liu, "Carrier mobility enhancement via strain engineering in future thin-body MOSFETs," IEEE Electron Device Letters, Vol. 33, No. 3, pp. 318-320, 2012.
    80. Y. Chen, R. Nathanael, J. Jeon, J. Yaung, L. Hutin, and T.-J. K. Liu, "Characterization of contact resistance stability in MEM relays with tungsten electrodes," IEEE/ASME Journal of Microelectromechanical Systems>, Vol. 21, No. 3, pp. 511-513, 2012.
    81. N. Damrongplasit, S. H. Kim, and T.-J. K. Liu, "Study of random dopant fluctuation induced variability in the raised-Ge-source TFET," IEEE Electron Device Letters, Vol. 34, No. 2, pp. 184-186, 2013.
    82. N. Damrongplasit, N. Xu, H. Takeuchi, R. J. Stephenson, N. W. Cody, A. Yiptong, X. Huang, M. Hytha, R. J. Mears and T.-J. K. Liu, "Comparative study of uniform vs. super-steep retrograde MOSFET channel doping and implications for 6-T SRAM yield," IEEE Transactions on Electron Devices, Vol. 60, No. 5, pp. 1790-1793, 2013.
    83. D. Fu, J. Zhou, S. Tongay, K. Liu, W. Fan, T.-J. K. Liu and J. Wu, "Mechanically modulated tunneling resistance in monolayer MoS2," Applied Physics Letters, Vol. 103, pp. 183105-1 to 183105-3, 2013.
    84. E. S. Park, Y. Chen, T. J. K. Liu, and V. Subramanian, “A new switching device for printed electronics: Inkjet-printed microelectromechanical relay,” Nano Letters, Vol. 13, No. 11, pp. 5355-5360, 2013.
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    CONFERENCE PRESENTATIONS
    Invited and Keynote:
    1. I-W. Wu, T.-J. King, M. Hack, C. C. Tsai, A. G. Lewis, and A. Chiang, "Leakage currents in polycrystalline silicon thin film transistors for liquid crystal displays," Proceedings of International Semiconductor Device Research Symposium, pp. 21-24, 1993.
    2. T.-J. King, "Trends in polycrystalline-silicon thin-film transistor technologies for AMLCDs," Proceedings of 2nd International Workshop on Active Matrix Liquid Crystal Displays, pp. 80-86, 1995.
    3. C. Chan, S. Qin, and T.-J. King, "Plasma ion implantation for flat panel displays," presented at the MRS 1996 Fall Meeting (Boston, Massachusetts, USA), December 1996.
    4. T.-J. King, "Status and prospect of silicon-germanium TFT technology for AMLCD application," Conference Record of the 1997 International Display Research Conference, pp. M29-M35, 1997.
    5. T.-J. King, "Polycrystalline silicon thin films for active-matrix flat-panel displays," presented at the 44th National Symposium of the American Vacuum Society (San Francisco, California, USA), October 1997.
    6. T.-J. King and Y.-J. Tung, "Low-temperature poly-Si TFT technology for lightweight, high-performance displays," Proceedings of the 1997 International Semiconductor Device Research Symposium (Charlottesville, Virginia, USA), pp. 451-454, 1997.
    7. S. Yamamichi, A. Yamamichi, D. Park, H. Yabuta, T. Iizuka, K. Arita, S. Sone, Y. Kato, S. Nishimoto, T.-J. King, C. Hu, and M. Yoshida, "Reliability study on high dielectric constant (Ba,Sr)TiO3 thin film," presented at the 193rd ECS Meeting (San Diego, California, USA), May 1998.
    8. T.-J. King, "Advanced gate technology for sub-0.25 micron CMOSFETs," presented at the SPIE 1998 Symposium on Microelectronic Manufacturing (Santa Clara, California, USA), September 1998.
    9. T.-J. King, "LSI on glass substrates," presented at LCD/PDP International ‘98 (Tokyo, Japan), October 1998.
    10. P. G. Carey, P. M. Smith, S. D. Theiss, P. Wickboldt, T. W. Sigmon, Y.-J. Tung and T.-J. King, "Poly-Si thin film transistors fabricated on plastic substrates," 11th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Conference Proceedings, pp. 126-127, 1998.
    11. T.-J. King, "Device design considerations for sub-50 nm CMOS," Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials (Tokyo, Japan), pp. 28-29, 1999.
    12. T.-J. King, "Thin-film transistor technologies for flexible, lightweight flat-panel displays," presented at the Association of Super-Advanced Electronics Technologies (ASET) International Forum on Low Power Displays (Tokyo, Japan), July 21, 2000.
    13. T.-J. King, "Poly-Si TFT technologies for future flat-panel displays," Conference Record of the 20th International Display Research Conference (Palm Beach, Florida, USA), pp. 406-410, 2000.
    14. T.-J. King, "Ultra-scaled MOSFETs for future nanoelectronics," presented at The First Korea-U.S.-Japan Workshop on Nanostructure Science and Technology (Seoul, Korea), April 2001.
    15. T.-J. King, "Materials Requirements for Future Thin-Body SOI CMOSFETs," presented at the MRS 2001 Fall Meeting, Symposium A: Materials Issues in Novel Si-Based Technology (Boston, Massachussetts, USA), November 2001.
    16. P. Ranade, Q. Lu, I. Polishchuk, H. Takeuchi, C. Hu, and T.-J. King, "Dual work function metal gate technology for future CMOS devices," presented at the 3rd International on Microelectronics and Interfaces (ICMI 2002) (Santa Clara, California, USA), February 2002.
    17. R. T. Howe and T.-J. King, "Low temperature LPCVD MEMS technologies," BioMEMS and Bionanotechnology Symposium, Materials Research Society Proceedings Vol.729 (Materials Research Society, Warendale, PA, USA), pp. 205-213, 2002.
    18. T.-J. King and R. T. Howe, "Interconnect issues for MEMS technology," presented at the Advanced Metallization Conference (San Diego, California, USA), October 2002.
    19. T.-J. King, "Gate material issues for high-k gate stacks," presented at the 33rd IEEE Interface Specialists Conference (San Diego, California, USA), December 2002.
    20. T.-J. King, R. T. Howe and S. Sedky "Recent progress in modularly integrated MEMS technologies," International Electron Devices Meeting Technical Digest, pp. 199-202, 2002.
    21. T.-J. King, "Advanced materials and processes for nanometer-scale FinFETs," Proceedings of the International Electron Devices and Materials Symposia (Taipei, Taiwan, R. O. C.), pp. 11-15, 2002.
    22. P. Ranade, Y.-K. Choi, D. Ha, H. Takeuchi, and T.-J. King, "Metal gate technology for fully depleted SOI CMOS," presented at the 4th International AVS Conference on Microelectronics and Interfaces (ICMI 2003) (Santa Clara, California, USA), March 2003.
    23. S. Balasubramanian, L. Chang, Y.-K. Choi, D. Ha, J. Lee, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, "Extremely scaled ultra-thin-body and FinFET CMOS devices," presented at the 11th International Symposium on SOI Device Technologies (Symposium J3, 203rd Meeting of the Electrochemical Society, Paris, France), April 2003.
    24. C. M. Osburn, S. K. Han, I. Kim, S. Campbell, E. Garfunkel, T. Gustafson, J. Hauser, T.-J. King, Q. Liu, P. Ranade, A. Kingon, D.-L. Kwong, S. J. Lee, C. H. Lee, J. Lee, K. Onishi, C. S. Kang, R. Choi, H. Cho, R. Nieh, G. Lucovsky, J. G. Hong, T. P. Ma, W. Zhu, Z. Luo, J. P. Maria, D. Wicaksana, V. Misra, J. J. Lee, Y. S. Suh, G. Parsons, D. Niu, and S. Stemmer, "Integration issues with high k gate stacks," ULSI Process Integration III, Electrochemical Society Proceedings Vol. 2003-6, pp. 373-390, 2003.
    25. Keynote (Plenary) Paper: T.-J. King, "Sustaining the Si revolution: challenges and opportunities," presented at the 2003 IEEE University/Government/Industry Microelectronics Symposium (Boise, Idaho, USA), June 2003.
    26. B. Nikolic, L. Chang, and T.-J. King, "Performance of deeply-scaled, power-constrained circuits," Extended Abstracts of the 2003 International Conference on Solid-State Devices and Materials (Tokyo, Japan), pp. 154-155.
    27. T.-J. King, "FinFET promise and challenges," Extended Abstracts of the 2003 International Conference on Solid-State Devices and Materials (Tokyo, Japan), pp. 280-281.
    28. H. Takeuchi and T.-J. King, "Process optimization and integration of HfO2 and Hf-Silicates," presented at the MRS 2004 Spring Meeting, Symposium D (San Francisco, California, USA), April 2004.
    29. H.-Y. Wong, H. Takeuchi, T.-J. King, M. Ameen, and A. Agarwal, "Reduced poly-Si gate depletion effect by pulsed excimer laser annealing," presented at the 205th ECS Meeting, Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II Symposium (San Antonio, TX, USA), May 2004.
    30. Keynote (Plenary) Paper: T.-J. King, "Taking silicon to the limit: challenges and opportunities," presented at the 2004 International Conference on Solid-State and Integrated-Circuit Technology (Beijing, China), October 2004.
    31. E. P. Quevy, T.-J. King, and R. T. Howe, "Integrated poly-SiGe nanomechanical resonators for wireless sensor nodes," Proc. SPIE, Vol. 5593, pp. 368-377, 2004.
    32. J. Lai and T.-J. King, "Recent developments in low-temperature poly-Si (LTPS) technology," presented at the International Display Manufacturing Conference (Taipei, Taiwan R.O.C.), February 2005.
    33. T.-J. King, "FinFETs for nanoscale CMOS digital integrated circuits," presented at the International Conference on Computer Aided Design (San Jose, California, USA), November 7, 2005.
    34. K. Shin, S. Balasubramanian, X. Sun, and T.-J. King, "Strain engineering and body biasing for optimization of sub-45nm CMOS performance," presented at the MRS 2006 Spring Meeting (San Francisco, California, USA), April 2006.
    35. H. Takeuchi, K. Shiraishi, and T.-J. K. Liu, "Role of oxygen states in high-k gate stack engineering," presented at the 8th International Conference on Solid-State and Integrated-Circuit  Technology (Shanghai, China), October 2006.
    36. K. Shiraishi, H. Takeuchi, Y. Akasaka, T. Nakayama, S. Miyazaki, T. Nakaoka, A. Ohta, H. Watanabe, N. Umezawa, K. Ohmori, P. Ahmet, T. Chikyow, Y. Nara, T.-J. K. Liu, H. Iwai, and K. Yamada, "Physics of interfaces between gate electrodes and high-k dielectrics,"  presented at the 8th International Conference on Solid-State and Integrated-Circuit Technology (Shanghai, China), October 2006.
    37. W. Xiong, C. R. Cleavelin, C.-H. Hsu, M. Ma, K. Schruefer, K. von Armin, T. Schulz, I. Cayrefourcq, C. Mazure, P. Patruno, M. Kennard, K. Shin, X. Sun, T.-J. K. Liu, K. Cherkaoui, and J. P. Colinge, "Intrinsic advantages of SOI multiple-gate MOSFET (MuGFET) for low power applications," 211th ECS Meeting (Chicago, Illinois, USA), May 2007.
    38. H.-H. Tseng, P. Kalra, J. Oh, P. Majhi, T.-J. K. Liu, and R. Jammy, "The challenges and progress of USJ formation & process integration for 32nm technology and beyond," 8th International Workshop on Junction Technology (Shanghai, China), May 2008.
    39. P. Kalra, P. Majhi, H.-H. Tseng, L. Larson, R. Jammy, and T.-J. K. Liu, "USJ process challenges for sub-45nm CMOS," 17th International Conference on Ion Implantation Technology (Monterey, California, USA), June 2008.
    40. H. Kam, T.-J. K. Liu, E. Alon, and M. Horowitz, "Circuit-level requirements for MOSFET-replacement devices," IEEE International Electron Devices Meeting Technical Digest, p. 427, 2008.
    41. T.-J. K. Liu, C. Shin, Z. Guo, M. H. Cho, B. Nikolic, and B.-Y. Nguyen, "SRAM cell design considerations for SOI technology," presented at the IEEE International SOI Conference (Foster City, California, USA), October 2009.
    42. B. Nikolic, C. Shin, M. H. Cho, X. Sun, T.-J. K. Liu, and B.-Y. Nguyen, "SRAM design in fully-depleted SOI technology," presented at the IEEE International Symposium on Circuits and Systems (Paris, France), May 2010.
    43. T.-J. K. Liu and S. H. Kim, "Tunnel FET promise and challenges," presented at the 2010 International Conference on Solid-State Devices and Materials (Tokyo, Japan), September 2010.
    44. T.-J. K. Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott, and E. Alon, "Prospects for MEM-relay logic switch technology," IEEE International Electron Devices Meeting Technical Digest, pp. 424-427, 2010.
    45. C. Hu, P. Patel, A. Bowonder, K. Jeon, S. Kim, W. Y. Loh, C. Y. Kang, J. Oh, P. Majhi, A. Javey, T-J. K. Liu, and R. Jammy, "Prospect of tunneling green transistor for 0.1V CMOS," IEEE International Electron Devices Meeting Technical Digest, pp. 387-390, 2010.
    46. T.-J. K. Liu, E. Alon, V. Stojanovic, and D. Markovic, "Mechanical computing redux: relays for integrated-circuit applications," presented at the Government Microcircuit Applications and Critical Technology Conference (Orlando, FL, USA), March 2011.
    47. T.-J. K. Liu, W. Y. Choi, and H. Kam, "Nano-Electro-Mechanical Memory (NEMory) technology promise and challenges," presented at the 2011 MRS Spring Meeting, Symposium Q (San Francisco, California, USA), April 2011.
    48. T.-J. K. Liu, S. H. Kim, and Z. A. Jacobson, "Ge-source TFETs for ultra-low-power electronics," presented at the 219th ECS Meeting, Symposium E3 (Montreal, Quebec, Canada), May 2011.
    49. A. R. Neureuther, J. Rubenstein, M. Miller, K. Yamazoe, E. Chin, C. Levy, L. Wang, N. Xu, C. Spanos, K. Qian, K. Poolla, J. Ghan, A. Subramanian, T.-J. K. Liu, X. Sun, K. Jeong, P. Gupta, A. Kaqalwalla, R. Ghaida, and T.-B. Chan, "Collaborative research on emerging technologies and design," in Proceedings of the Symposium on Photomask and Next Generation Lithography Mask Technology (Photomask Japan), 2011.  
    50. Plenary Paper: T.-J. K. Liu, "Electronics proliferation through diversification," presented at the 2011 International Conference on Solid-State Devices and Materials (Nagoya, Japan), September 2011.
    51. T.-J. K. Liu, P. Matheu, Z. Jacobson, and S. H. Kim, "Steep-subthreshold-slope devices on SOI," presented at the 2011 IEEE International SOI Conference (Tempe, Arizona, USA), October 2011.
    52. T.-J. K. Liu, L. Hutin, I-R. Chen, R. Nathanael, Y. Chen, and E. Alon, "Recent progress and challenges for relay logic switch technology," presented at the 2012 Symposium on VLSI Technology (Honolulu, Hawaii, USA), June 2012.
    53. N. Xu, C. Shin, F. Andrieu, B. Ho, O. Weber, W. Xiong, T. Poiroux, B.-Y. Nguyen, V. Moroz, O. Faynot and T.-J. K. Liu, "The effectiveness of strain solutions in next-generation MOSFETs," presented at the IEEE International SOI Conference (Napa, California, USA), October 2012.
    54. H. Kam, Y. Chen and T.-J. K. Liu, "Reliable micro-electro-mechanical (MEM) switch design for ultra-low power logic," presented at the 2013 IEEE International Reliability Physics Symposium (Monterey, California, USA), April 2013.
    55. T.-J. K. Liu, N. Xu, I-R. Chen, C. Qian and J. Fujiki,” NEM relay design for compact, ultra-low-power digital logic circuits,” to be presented at the 2014 International Electron Devices Meeting (San Francisco, California, USA), December 2014.
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    Regular:
    1.  S. Wood, P. Apte, T.-J. King, M. Moslehi, and K. Saraswat, "Pyrometer modeling for rapid thermal processing," Proceedings of the SPIE --The International Society of Optical Engineering, Vol. 1393, pp. 337-348, 1990.
    2. T.-J. King, J. R. Pfiester, J. D. Shott, J. P. McVittie, and K. C. Saraswat, "A polycrystalline-Si1-xGex-gate CMOS technology," International Electron Devices Meeting Technical Digest, pp. 253-256, 1990.
    3. T.-J. King and K. C. Saraswat, "A low-temperature (<550oC) silicon-germanium MOS thin-film transistor technology for large-area electronics," International Electron Devices Meeting Technical Digest, pp. 567-570, 1991.
    4. M. Hack, I-W. Wu, A. G. Lewis, and T.-J. King, "Numerical simulations of poly-crystalline silicon thin film transistors including leakage effects," IEE Colloquium on Poly-Si Devices and Applications, IEE Digest No. 1993/067, pp. 23/1-23/4, 1993.
    5. M. Hack, I-W. Wu, A. Lewis, and T.-J. King, "Numerical simulations of ON and OFF state characteristics of poly-silicon thin film transistors," IEEE Transactions on Electron Devices, Vol. 40, No. 11, p. 2128, 1993 (presented at the 51st Annual Device Research Conference).
    6. S. Jurichich, T.-J. King, K. Saraswat, and J. Mehlhaff, "A low-thermal-budget polycrystalline silicon-germanium thin-film transistor technology for large-area electronics," Proceedings of International Semiconductor Device Research Symposium, pp. 55-58, 1993.
    7. M. Hack, I-W. Wu, T.-J. King, and A. G. Lewis, "Analysis of leakage currents in poly-silicon thin film transistors," International Electron Devices Meeting Technical Digest, pp. 385-388, 1993.
    8. T.-J. King and M. Hack, "Two-dimensional drain engineering for leakage reduction in thin-film transistors," 52nd Annual Device Research Conference Digest, p. IIIA-5, 1994.
    9. J. D. Bernstein, S. Qin, C. Chan, and T.-J. King, "A study of process conditions for plasma ion implantation hydrogenation experiments," presented at the IEEE International Conference on Plasma Science (Madison, Wisconsin, USA), June 1995.
    10. E. Cheng, J. C. Sturm, I-W. Wu, and T.-J. King, "Modeling of leakage current distributions in series connected polysilicon thin film transistors," Proceedings of 2nd International Workshop on Active Matrix Liquid Crystal Displays, pp. 102-105, 1995.
    11. S. Qin, J. D. Bernstein, Y. Zhou, W. Liu, C. Chan, and T.-J. King, "Short-time hydrogen passivation of poly-Si CMOS thin film transistors by high dose rate plasma ion implantation," Ion-Solid Interactions for Materials Modifications and Processing, MRS Symposium Proceedings Vol. 396, pp. 515-520, 1995.
    12. A. J. Tang, J. A. Tsai, R. Reif, and T.-J. King, "A novel poly-Si-capped poly-Si1-xGex thin-film transistor," International Electron Devices Meeting Technical Digest, pp. 513-516, 1995.
    13. H. Y. Tong, T.-J. King, and F. G. Shi, "Crystallization of amorphous SiGe thin films," Thin Solid Films, Vol. 290-291, pp. 464-468, 1996 (presented at the International Conference on Metallurgical Coatings and Thin Films (San Diego, California, USA), April 1996).
    14. L. M. Lust, T.-J. King, I-W. Wu, and W. B. Jackson, "Telegraph noise as a probe of defects in thin film transistors," presented at the MRS 1996 Spring Meeting (San Francisco, California, USA), April 1996.
    15. V. Suntharalingam, S. J. Fonash, and T.-J. King, "A comprehensive study of the electrical stress stability of n-channel poly-Si TFTs," Proceedings of the SID 16th International Display Research Conference, pp. 283-285, 1996.
    16. V. Suntharalingam, S. J. Fonash, and T.-J. King, "A comprehensive study of the electrical stress stability of n-channel poly-Si TFTs," Proceedings of the Third Symposium on Thin Film Transistor Technologies, pp. 260-268, 1997 (presented at the ECS 1996 Fall Meeting, San Antonio, Texas, USA).
    17. K. C. Saraswat, S. Jurichich, T.-J. King, V. Subramanian, and A. Wang, "A low temperature polycrystalline SiGe CMOS TFT technology for large area AMLCD drivers," Proceedings of the Third Symposium on Thin Film Transistor Technologies, pp. 186-196, 1997 (presented at the ECS 1996 Fall Meeting, San Antonio, Texas, USA).
    18. Y. Zhou, S. Qin, C. Chan, and T.-J. King, "Investigation of plasma immersion ion implantation hydrogenation for poly-Si TFTs using an ICP plasma source," presented at the MRS 1996 Fall Meeting (Boston, Massachusetts, USA), December 1996.
    19. H. Y. Tong, Q. Jiang, D. Hsu, T.-J. King, and F. G. Shi, "Microstructural evolution of amorphous Si1-xGex thin films," Polycrystalline Thin Films -- Structure, Texture, Properties and Applications III, pp. 397-402, 1997 (presented at the MRS 1997 Spring Meeting, San Francisco, California, USA, April 1997).
    20. B. Yu, D.-H. Ju, N. Kepler, T.-J. King, and C. Hu, "Gate engineering for performance and reliability in deep-submicron CMOS technology," Symposium on VLSI Technology Digest of Technical Papers, pp. 105-106, 1997.
    21. B. Yu, T.-J. King, C. Hu, D.-H. Ju, and N. Kepler, "CMOS transistor reliability and performance impacted by gate microstructure," IEEE International Integrated Reliability Workshop Final Report, pp. 35-41, 1997.
    22. Best Student Paper Award: W.-C. Lee, A. Wang, T.-J. King, and C. Hu, "Impact of poly-Si0.8Ge0.2-gate technology on device performance and reliability," Proceedings of the 1997 International Semiconductor Device Research Symposium, pp. 513-516, 1997.
    23. B. Yu, Y.-J. Tung, S. Tang, E. Hui, T.-J. King, and C. Hu, "Ultra-thin-body silicon-on-insulator MOSFETs for terabit-scale integration," Proceedings of the 1997 International Semiconductor Device Research Symposium, pp. 623-626, 1997.
    24. Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, X. Meng, R. Weiss, G. A. Davis, V. Aebi, and T.-J. King, "An ultra-low-temperature-fabricated poly-Si TFT with stacked composite ECR-PECVD gate oxide," SID International Symposium Digest of Technical Papers, Vol. 29, pp. 887-890, 1998.
    25. D. Park, M. Kennard, Y. Melaku, N. Benjamin, T.-J. King, and C. Hu, "Stress-induced leakage current due to charging damage: gate oxide thickness and gate poly-Si etching condition dependence," Proceedings of the 1998 3rd International Symposium on Plasma Process-Induced Damage, pp. 56-59, 1998.
    26. W.-C. Lee, T.-J. King, and C. Hu, "Optimized poly-Si1-xGex-gate technology for dual gate CMOS application," 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 190-191, 1998.
    27. Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, X. Meng, R. Weiss, G. A. Davis, V. Aebi, and T.-J. King, "A high-performance poly-Si TFT technology compatible with flexible plastic substrates," presented at the 56th Annual Device Research Conference (Charlottesville, Virginia, USA), June 1998.
    28. Y.-J. Tung, J. Boyce, J. Ho, X. Huang, and T.-J. King, "A comparative study of hydrogen and deuterium plasma treatment effects on the performance and reliability of polysilicon TFTs," presented at the 56th Annual Device Research Conference (Charlottesville, Virginia, USA), June 1998.
    29. Y. Lee, R. A. Gough, T.-J. King, Q. Ji, K. N. Leung, R. A. McGill, V. V. Ngo, M. D. Williams, and N. Zahir, "Maskless ion beam lithography system," presented at Micro- and Nano-Engineering ‘98 (Leuven, Belgium), September 1998.
    30. Y.-C. King, T.-J. King, and C. Hu, "MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex," International Electron Devices Meeting Technical Digest, pp. 115-118, 1998.
    31. S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W. Sigmon, Y.-J. Tung, and T.-J. King, "Polysilicon thin film transistors fabricated at 100oC on a flexible plastic substrate," International Electron Devices Meeting Technical Digest, pp. 257-260, 1998.
    32. D. Park, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay, and C.-C. Cheng, "SiON/Ta2O5/TiN gate stack transistor with 1.8 nm equivalent SiO2 thickness," International Electron Devices Meeting Technical Digest, pp. 381-384, 1998.
    33. M. Krishnan, Y.-C. Yeo, Q. Lu, T.-J. King, J. Bokor, and C. Hu, "Remote charge scattering in MOSFETs with ultra-thin gate dielectrics," International Electron Devices Meeting Technical Digest, pp. 571-574, 1998.
    34. Y.-C. King, C. Kuo, T.-J. King, and C. Hu, "Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation," International Electron Devices Meeting Technical Digest, pp. 585-588, 1998.
    35. D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor, and C. Hu, "A folded-channel MOSFET for deep-sub-tenth micron era," International Electron Devices Meeting Technical Digest, pp. 1032-1034, 1998.
    36. A. E. Franke, D. T. Chang, P. T. Jones, T.-J. King, R. T. Howe, and G. C. Johnson, "Post-CMOS integration of germanium microstructures," Twelfth IEEE International Conference on Micro Electro Mechanical Systems, pp. 630-637, 1999.
    37. H. Takeuchi and T.-J. King, "Poly-Si1-xGex process integration for low sheet resistance gate CMOS technology," Advances in Rapid Thermal Processing. Proceedings of the Symposium (Seattle, Washington, USA), Electrochemical Society Proceeding Vol. 99-10, pp. 277-284, 1999.
    38. Y. Lee, R. A. Gough, T.-J. King, Q. Ji, and K.-N. Leung, "Maskless ion beam lithography system," Microelectronic Engineering, Vol. 46, pp. 469-472, May 1999.
    39. Y.-J. Tung, J. Ho, J. Boyce, X. Huang, and T.-J. King, "Improved DC reliability of polysilicon thin-film transistors with deuterium plasma treatment," SID International Symposium Digest of Technical Papers, pp. 398-401, 1999.
    40. Q. Ji, T.-J. King, Y. Y. Lee, and K.-N. Leung, "Compact column design for a focused ion beam lithography system," Proceedings of the SPIE, Vol. 3777, pp. 175-182, 1999.
    41. J. M. Heck, Chris G. Keller, A. E. Franke, Lilac Muller, R. T. Howe, and T.-J. King, "High aspect ratio poly-silicon-germanium microstructures," in Proceedings of the 1999 International Conference on Solid-State Sensors and Actuators -- Transducers ‘99 (Sendai, Japan), pp. 328-331, 1999.
    42. A. E. Franke, D. Bilic, D. T. Chang, P. T. Jones, T.-J. King, R. T. Howe, and G. C. Johnson, "Optimization of poly-silicon-germanium as a microstructural material," in Proceedings of the 1999 International Conference on Solid-State Sensors and Actuators -- Transducers ‘99 (Sendai, Japan), pp. 530-533, 1999.
    43. V. Subramanian, J. Kedzierski, N. Lindert, H. Tam, Y. Su, J. McHale, K. Cao, T.-J. King, J. Bokor, and C. Hu, "A bulk-Si-compatible ultrathin-body SOI technology for sub-100 nm MOSFETs," 57th Annual Device Research Conference Digest, pp. 28-29, 1999.
    44. W.-C. Lee, T.-J. King, and C. Hu, "Performance enhancement in deep-submicron poly-SiGe-gated CMOS devices," 1999 International Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical Papers, pp. 14-18, 1999.
    45. Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C. Hu, "Nanoscale SiGe-channel ultra-thin-body silicon-on-insulator P-MOSFETs," 1999 International Semiconductor Device Research Symposium Proceedings, pp. 295-298, 1999.
    46. Q. Lu, Y. C. Yeo, K. Yang, R. Lin, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, X. Guo, X. Wang, and T.-P. Ma, "Comparison of 14A TOX,EQ JVD and RTCVD silicon nitride gate dielectrics for sub-100 nm MOSFETs," 1999 International Semiconductor Device Research Symposium Proceedings, pp. 489-492, 1999.
    47. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS," International Electron Devices Meeting Technical Digest, pp. 67-70, 1999.
    48. M. S. Krishnan, L. Chang, T.-J. King, J. Bokor, and C. Hu, "MOSFETs with 9 to 13 A Thick Gate Oxides," International Electron Devices Meeting Technical Digest, pp. 241-244, 1999.
    49. H. Takeuchi, W.-C. Lee, P. Ranade, and T.-J. King, "Improved PMOSFET short-channel performance using ultra-shallow Si0.8Ge0.2 source/drain extensions," International Electron Devices Meeting Technical Digest, pp. 501-504, 1999.
    50. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultrathin-body SOI MOSFET for deep-sub-tenth micron era," International Electron Devices Meeting Technical Digest, pp. 919-921, 1999.
    51. P. Ranade, Y.-C. Yeo, Q. Lu, H. Takeuchi, T.-J. King, and C. Hu, "Molybdenum as a gate electrode for deep sub-micron CMOS technology," presented at the MRS 2000 Spring Meeting (San Francisco, California, USA), April 2000.
    52. Q. Ji, T.-J. King, Y. Y. Lee, and K.-N. Leung, "Maskless direct-write lithography using focused O2+ beam," presented at the 44th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Palm Springs, California, USA), June 2000.
    53. K. L. Scott, T.-J. King, and K.-N. Leung, "Microfabrication of pattern generators and microcolumns for ion beam lithography," presented at the 44th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Palm Springs, California, USA), June 2000.
    54. A. E. Franke, Y. Jiao, M. T. Wu, T.-J. King, and R. T. Howe, "Post-CMOS modular integration of poly-SiGe microstructures using poly-Ge sacrificial layers," Solid-State Sensor and Actuator Workshop Technical Digest, pp. 18-21, June 2000.
    55. Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, and C. Hu, "30nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D," 58th Annual Device Research Conference Digest, pp. 23-24, 2000.
    56. Y. C. Yeo, Q. Lu, W.-C. Lee, T.-J. King, and C. Hu, "Scaling limit of silicon nitride gate dielectric for future CMOS technologies," 58th Annual Device Research Conference Digest, pp. 65-66, 2000.
    57. P. Xuan, J. Kedzierski, V. Subramanian, J. Bokor, T.-J. King and C. Hu, "60nm planarized ultra-thin body solid phase epitaxy MOSFETs," 58th Annual Device Research Conference Digest, pp. 67-68, 2000.
    58. J. Kedzierski, P. Xuan, V. Subramanian, J. Bokor, T.-J. King, C. Hu, and E. A. Anderson, "20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain," Superlattices and Microstructures, Vol.28, No.5-6, p.445-52, 2000 (presented at the 5th Silicon Nanoelectronics Workshop, Honolulu, HI, USA, 11-12 June 2000.)
    59. Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T.-J. King, and C. Hu, "Dual-metal gate technology for deep-submicron CMOS transistors," 2000 Symposium on VLSI Technology, Digest of Technical Papers, pp. 72-73, 2000.
    60. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime," International Electron Devices Meeting Technical Digest, pp. 57-60, 2000.
    61. Q. Lu, R. Lin, P. Ranade, Y. C. Yeo, X. Meng, H. Takeuchi, T.-J. King, C. Hu, H. Luan, S. Lee, W. Bai, C.-H. Lee, D.-L. Kwong, X. Guo, X. Wang, and T.-P. Ma, "Molybdenum metal gate MOS technology for post-SiO2 gate dielectrics," International Electron Devices Meeting Technical Digest, pp. 641-644, 2000.
    62. L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," International Electron Devices Meeting Technical Digest, pp. 719-722, 2000.
    63. X. Huang, Y. Cao, D. Sylvester, S. Lin, T.-J. King, and C. Hu, "RLC signal integrity analysis of high-speed global interconnect," International Electron Devices Meeting Technical Digest, pp. 731-734, 2000.
    64. Y.-C. Yeo, Q. Lu, T.-J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro, and J. Sakai, "Enhanced performance in sub-100nm CMOSFETs using strained epitaxial silicon-germanium," International Electron Devices Meeting Technical Digest, pp. 753-756, 2000.
    65. Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, P. Wickboldt, X. Meng, R. E. Weiss, G. A. Davis, V. W. Aebi, and T.-J. King, "Polycrystalline silicon thin-film transistor technology for flexible large-area electronics," Proceedings of SPIE, Vol. 4295: Flat Panel Display Technology and Display Metrology II, Paper 4295A-15, 2001.
    66. I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King, and C. Hu, "Hot-carrier reliability of P-MOSFET with ultra-thin silicon nitride gate dielectric," presented at the International Reliability Physics Symposium (Orlando, Florida, USA), April 2001.
    67. S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "FinFET -- a quasi-planar double-gate MOSFET," 2001 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 118-119, 2001.
    68. J. Reijonen, Q. Ji, T.-J. King, K.-N. Leung, A. Persaud, and S. Wilde, "Compact focusing system for ion and electron beams," presented at the 45th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Washington, D.C., USA), May 2001.
    69. K. L. Scott, T.-J. King, K.-N. Leung and R. F. Pease, "Characterization of multicusp-plasma ion source brightness using micron-scale apertures," presented at the 45th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Washington, D.C., USA), May 2001.
    70. Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, "Ultra-thin body PMOSFETs with selectively deposited Ge source/drain," 2001 Symposium on VLSI Technology, Digest of Technical Papers, pp. 19-20, 2001.
    71. Q. Lu, R. Lin, P. Ranade, T.-J. King, and C. Hu, "Metal gate work function adjustment for future CMOS technology," 2001 Symposium on VLSI Technology, Digest of Technical Papers, pp. 45-46, 2001.
    72. Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King, and C. Hu, "Effects of high-k dielectrics on the workfunctions of metal and silicon gates," 2001 Symposium on VLSI Technology, Digest of Technical Papers, pp. 49-50, 2001.
    73. I. Polishchuk, T.-J. King, and C. Hu, "Physical origin of SILC and noisy breakdown in very thin silicon nitride gate dielectric," presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
    74. Best Student Paper Award: N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, "Quasi-planar NMOS FinFETs with sub-100nm gate lengths," 59th Annual Device Research Conference Digest, pp. 26-27, 2001.
    75. Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, "Threshold voltage shift by quantum confinement in ultra-thin body device," 59th Annual Device Research Conference Digest, pp. 85-86, 2001.
    76. M. She, Y.-C. King, T.-J. King, and C. Hu, "Modeling and design study of nanocrystal memory devices," presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
    77. J. Kedzierski, M. Ieong, P. Xuan, J. Bokor, T.-J. King, and C. Hu, "Design analysis of thin-body silicide source/drain devices," 2001 IEEE International SOI Conference Proceedings, pp. 21-22, 2001.
    78. N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, "Quasi-planar FinFETs with selectively grown germanium raised source/drain," 2001 IEEE International SOI Conference Proceedings, pp. 111-112, 2001.
    79. L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King, and C. Hu, "Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs," International Electron Devices Meeting Technical Digest, pp. 99-102, 2001.
    80. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "Sub-20nm CMOS FinFET technologies," International Electron Devices Meeting Technical Digest, pp. 421-424, 2001.
    81. Q. Lu, R. Lin, H. Takeuchi, T.-J. King, C. Hu, K. Onishi, R. Choi, C.-S. Kang, and J. C. Lee, "Deep-submicron CMOS process integration of HfO2 gate dielectric with poly-Si gate," 2001 International Semiconductor Device Research Symposium Proceedings, pp. 377-380, 2001.
    82. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, "Dual work function metal gate CMOS transistors fabricated by Ni-Ti interdiffusion," 2001 International Semiconductor Device Research Symposium Proceedings, pp. 411-415, 2001.
    83. 2nd Best Student Paper Award: Y.-K. Choi, T.-J. King, and C. Hu, "Spacer FinFET: Nano-scale CMOS technology for the terabit era," 2001 International Semiconductor Device Research Symposium Proceedings, pp. 543-546, 2001.
    84. M. She, T.-J. King, C. Hu, W. Zhu, Z. Luo, J.-P. Han, and T.-P. Ma, "Low-voltage, fast-programming p-channel flash memory with JVD tunneling nitride," 2001 International Semiconductor Device Research Symposium Proceedings, pp. 641-644, 2001.
    85. Q. Lu, T.-J. King, and C. Hu, "Hot carrier reliability of n-MOSFET with ultra-thin HfO2 gate dielectric and poly-Si gate," presented at the International Reliability Physics Symposium (Dallas, Texas, USA), April 2002.
    86. P. Ranade, R. Lin, Q. Lu, Y.-C. Yeo, H. Takeuchi, T.-J. King, and C. Hu, "Molybdenum gate electrode technology for deep sub-micron CMOS generations," Gate Stack and Silicide Issues in Silicon Processing II Symposium, Materials Research Society Symposium Proceedings Vol.670 (Materials Research Society, Warendale, PA, USA), pp. K5.2.1-6, 2002.
    87. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, "Dual work function CMOS gate technology based on metal interdiffusion," Gate Stack and Silicide Issues in Silicon Processing II Symposium, Materials Research Society Symposium Proceedings Vol.670 (Materials Research Society, Warendale, PA, USA), pp. K5.1.1-6, 2002.
    88. X. Huang, P. Restle, T. Bucelot, Y. Cao, and T.-J. King, "Loop-based interconnect modeling and optimization approach for multi-GHz clock network design," presented at the Custom Integrated Circuits Conference (Orlando, Florida, USA), May 2002.
    89. Y. Cao, R. A. Groves, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, X. Huang, T.-J. King, and C. Hu, "Frequency-independent equivalent circuit model for on-chip spiral inductors," Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, pp. 217-220, 2002.
    90. Q. Ji, X. Jiang, T.-J. King, K.-N. Leung, and K. Standiford, "Improvement of brightness for multicusp-plasma ion source," presented at the 46th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Anaheim, California, USA), May 2002.
    91. S. A. Bhave, B. L. Bircumshaw, W. Z. Low, Y.-S. Kim, T.-J. King, R. T. Howe, and A. P. Pisano, "Poly-SiGe: A high-Q structural material for integrated RF MEMS," Solid-State Sensor and Actuator Workshop, Technical Digest, pp. 34-37, 2002.
    92. Q. Lu, H. Takeuchi, R. Lin, T. King, C. Hu, K. Onishi, R. Choi, C. Kang and J. Lee,  "Hot Carrier Reliability of n-MOSFET with Ultra-thin HfO2 Gate Dielectric and Poly-Si Gate," International Reliability Physics Symposium Proceedings, p. 429-430, 2002.
    93. Q. Lu, H. Takeuchi, X. Meng, T.-J. King, C. Hu, K. Onishi, H.-J. Cho, and J. Lee, "Improved performance of ultra-thin HfO2 CMOSFETs using poly-SiGe gate," 2002 VLSI Symposium on Technology, Digest of Technical Papers, pp. 86-87, 2002.
    94. I. Polishchuk, K. J. Yang, T.-J. King, and C. Hu, "Improved MOSFET electron mobility for advanced gate dielectric stacks," 60th Annual Device Research Conference, Conference Digest, pp. 75-76, 2002.
    95. I. Polishchuk, Y.-C. Yeo, T.-J. King, and C. Hu, "Tunneling through multi-layer gate dielectrics - an analytical model," 60th Annual Device Research Conference, Conference Digest, pp. 105-106, 2002.
    96. Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, "Reduction of gate-induced drain leakage (GIDL) current in single-gate ultra-thin body and double-gate FinFET devices," presented at the 2002 International Conference on Solid State Devices and Materials (Nagoya, Japan), September 2002.
    97. D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King, and C. Hu, "Ultra thin body silicon-on-insulator (UTB SOI) MOSFET with metal gate work-function engineering for sub-70nm technology node," presented at the 2002 International Conference on Solid State Devices and Materials (Nagoya, Japan), September 2002.
    98. K.-J. Yang, H. Takeuchi, T.-J. King, and C. Hu, "Frequency dependence of capacitance measurement for advanced gate dielectrics," presented at the 2002 International Conference on Solid State Devices and Materials (Nagoya, Japan), September 2002.
    99. Y. Cao, X. Huang, D. Sylvester, T.-J. King, and C. Hu, "Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design," presented at the 15th Annual IEEE International ASIC/SOC Conference (Rochester, New York, USA), September 2002.
    100. X. Huang, Y. Cao, T.-J. King, and C. Hu, "Analytical performance models for RLC interconnects and application to clock optimization," presented at the 15th Annual IEEE International ASIC/SOC Conference (Rochester, New York, USA), September 2002.
    101. H. Takeuchi and T.-J. King, "Investigation of interface properties of CVD HfO2 by SCA (Surface Charge Analysis)," presented at the International SEMATECH Gate Stack Engineering Working Group Symposium (Austin, Texas, USA), October 16, 2002.
    102. S. Sedky, J. Schroeder, T. Sands, R. Howe, and T.-J. King, "Pulsed laser annealing of silicon-germanium films," presented at the MRS 2002 Fall Meeting, Symposium J (Boston, Massachusetts, USA), December 2002.
    103. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Hu, T.-J. King, J. Bokor, M.-R. Lin, and D. Kyser, "FinFET scaling: towards 10nm gate length," International Electron Devices Meeting Technical Digest, pp. 251-254, 2002.
    104. Y.-K. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, T.-J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," International Electron Devices Meeting Technical Digest, pp. 259-262, 2002.
    105. P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable-work-function molybdenum gate technology for FDSOI-CMOS," International Electron Devices Meeting Technical Digest, pp. 363-366, December 2002.
    106. C. Kuo, T.-J. King, and C. Hu, "A capacitorless double-gate DRAM cell design for high density applications," International Electron Devices Meeting Technical Digest, pp. 843-846, 2002.
    107. H. Takeuchi, P. Ranade, and T.-J. King, "Low-temperature dopant activation technology using elevated Ge-S/D structure," presented at the First International SiGe Technology and Device Meeting (Nagoya, Japan), pp. 163-164, 2003.
    108. M. She and T.-J. King, "Improved SONOS-type flash memory using HfO2 as trapping layer," presented at the 19th IEEE Non-Volatile Semiconductor Memory Workshop (Monterey, California, USA), pp. 53-55, 2003.
    109. D. Ha, Q. Lu, H. Takeuchi, T.-J. King, K. Onishi, Y.-H. Kim, and J. C. Lee, "Impact of gate process technology on EOT of HfO2 gate dielectric," MRS Symposium Proceedings Vol. 765, pp. 41-45, 2003 (presented at the MRS 2003 Spring Meeting, Symposium D, April 2003).
    110. R. Yamada and T.-J. King, "Variable stress-induced leakage current and analysis of anomalous charge loss for flash memory operation," 2003 IEEE International Reliability Physics Symposium Proceedings, pp. 491-496, 2003.
    111. S. Balasubramanian, L. Chang, B. Nikolic, and T.-J. King, "Circuit-performance implications for double-gate MOSFET scaling below 25 nm," Proceedings of the 2003 Silicon Nanoelectronics Workshop, pp. 16-17, June 2003.
    112. H. Takeuchi, M. She, K. Watanabe, and T.-J. King, "Damageless sputter deposition for metal gate CMOS technology," 61st Annual Device Research Conference Digest, pp. 35-36, 2003.
    113. M. She, H. Takeuchi, and T.-J. King, "SONNS memory: improvement over SONOS flash memory," 61st Annual Device Research Conference Digest, pp. 55-56, 2003.
    114. B. Bircumshaw, G. Liu, H. Takeuchi, T.-J. King, R. Howe, O. O'Reilly, and A. Pisano, "The radial bulk annular resonator:  towards a 50W RF MEMS filter," Proceedings of the 12th International Conference on Solid-State Sensors, Actuators, and Microsystems (Transducers ’03), pp. 875-878, 2003.
    115. A. Yagishita, T.-J. King, and J. Bokor, "Schottky barrier height reduction and drive current improvement in metal source/drain MOSFET with strained-Si channel," Extended Abstracts of the 2003 International Conference on Solid-State Devices and Materials, pp. 708-709.
    116. H. Takeuchi, D. Ha, and T.-J. King, "Observation of bulk HfO2 defects by spectroscopic ellipsometry," presented at the AVS 50th International Symposium, Topical Conference on High-K Gate Dielectrics and Devices (Baltimore, MD, USA), November 2003.
    117. B. C.-Y. Lin, T.-J. King, and R. T. Howe, "Optimization of poly-SiGe deposition processes for integrated MEMS," presented at the MRS 2003 Fall Meeting, Symposium A (Boston, MA, USA), November 2003.
    118. K. Buchheit, H. Takeuchi, and T.-J. King, "Properties of ultra-thin silicon nitride barriers," presented at the MRS 2003 Fall Meeting, Symposium E (Boston, MA, USA), November 2003.
    119. M.-A. Eyoum, E. Quevy , H. Takeuchi, T.-J. King, and R.T. Howe, "Ashing technique for nano-gap fabrication of electrostatic transducers," presented at the MRS 2003 Fall Meeting, Symposium M (Boston, MA, USA), November 2003.
    120. Y.-K. Choi, D. Ha, J. Bokor, and T.-J. King, "Reliability study of CMOS FinFETs," International Electron Devices Meeting Technical Digest, pp. 177-180, 2003.
    121. P. Xuan, M. She, J. Bokor, and T.-J. King, "FinFET SONOS flash memory for embedded applications," International Electron Devices Meeting Technical Digest, pp. 609-612, 2003.
    122. J. Fossum, M. M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, "Physical insights on design and modeling of nanoscale FinFETs," International Electron Devices Meeting Technical Digest, pp. 679-283, 2003.
    123. B. L. Bircumshaw, M. L. Wasilik, E. B. Kim, Y. R. Su, H. Takeuchi, C. W. Low, G. Liu, A. P. Pisano, T.-J. King, and R. T. Howe, "Hydrogen peroxide etching and stability of p-type poly-SiGe films," presented at the 17th IEEE Micro Electro Mechanical Systems Conference (Maastricht, The Netherlands), January 2004.
    124. C. F. H. Gondran, E. Morales, A. Guerry, W. Xiong, C. R. Cleavelin, R. Wise, S. Balasubramanian, and T.-J. King, "Fin sidewall micro-roughness measurement by AFM," presented at the MRS 2004 Spring Meeting, Symposium E (San Francisco, California, USA), April 2004.
    125. E. P. Quevy, S. A. Bhave, H. Takeuchi, T.-J. King, and R. T. Howe, "Poly-SiGe high frequency resonators based on lithographic definition of nano-gap lateral transducers," presented at Hilton Head 2004: A Solid State Sensor, Actuator and Microsystems Workshop (Hilton Head Island, South Carolina, USA), June 2004.
    126. M.-A. N. Eyoum, Y. R. Su, B. L. Bircumshaw, D. Kouzminov, H. Takeuchi, R. T. Howe, and T.-J. King, "Effects of boron concentration on Si1-xGex properties for integrated MEMS technology," presented at Hilton Head 2004: A Solid State Sensor, Actuator and Microsystems Workshop (Hilton Head Island, South Carolina, USA), June 2004.
    127. H. Kam, L. Chang, and T.-J. King, "Impact of 3D source-drain doping profiles and contact schemes on FinFET performance in the nanoscale regime," Proceedings of the 2004 Silicon Nanoelectronics Workshop, pp. 9-10, 2004.
    128. C. W. Low, M. L. Wasilik, H. Takeuchi, T.-J. King, and R. T. Howe, "In-situ doped poly-SiGe LPCVD process using BCl3 for post-CMOS integration of MEMS devices," presented at the Symposium on SiGe: Materials, Processing, and Devices (part of the 2004 Joint International Meeting of The Electrochemical Society, The Electrochemical Society of Japan and The Japan Society of Applied Physics), (Honolulu, Hawaii, USA), October 2004.
    129. S. Balasubramanian, J. L. Garrett, V. Vidya, B. Nikolic, and T.-J. King, "Energy-delay optimization of thin-body MOSFETs for the sub-15nm regime," 2004 IEEE International SOI Conference Digest, pp. 27-29, 2004.
    130. W. Xiong, C. R. Cleavelin, R. Wise, S. Yu, M. Pas, R. J. Zaman, M. Gostkowski, K. Matthews, C. Maleville, P. Patruno, T.-J. King, and J. P. Colinge, "Full/partial depletion effects in FinFETs," presented at the 2004 IEEE International SOI Conference (Charleston, South Carolina, USA), October 2004.
    131. C. W. Low, B. L. Bircumshaw, T. Dorofeeva, G. Solomon, T.-J. King, and R. T. Howe, "Stress stability of poly-SiGe and various oxide films in humid environments," presented at the 2004 MRS Fall Meeting, Symposium U: Stability of Thin Films and Nanostructures (Boston, Massachusetts, USA), November 2004.
    132. D. Ha, H. Takeuchi, Y.-K. Choi, T.-J. King, W. Bai, D.-L. Kwong, A. Agarwal, and M. Ameen, "Molybdenum-gate HfO2 CMOS FinFET technology," International Electron Devices Meeting Technical Digest, pp. 643-646, 2004.
    133. H. Takeuchi, H. Y. Wong, D. Ha, and T.-J. King, "Impact of oxygen vacancies on high-k gate dielectric engineering," International Electron Devices Meeting Technical Digest, pp. 829-832, 2004.
    134. H. Y. Wong, H. Takeuchi, A. Padilla, T.-J. King, M. Ameen, and A. Agarwal, "Pulsed excimer laser annealing for meeting near-term front end processes gate-stack challenges," presented at the 207th Meeting of the Electrochemical Society, Symposium K1 (Quebec City, Canada), May 2005.
    135. A. Carlson and T.-J. King, "Multiple-drain transistors for reconfigurable applications," presented at the 2005 Device Research Conference (Santa Barbara, California, USA).
    136. K. Shin, T. Lauderdale, and T.-J. King, "Effect of tensile capping layer on 3-D stress profiles in FinFET channels," presented at the 2005 Device Research Conference (Santa Barbara, California, USA).
    137. Best Paper Award: Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, and Borivoje Nikolic, "FinFET-based SRAM design," presented at the International Symposium on Low Power Electronics and Design (San Diego, California, USA), pp. 2-7, August 2005.
    138. H. Kam, D. Lee, R. T. Howe, and T.-J. King, "A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics," IEEE International Electron Devices Meeting Technical Digest, pp. 477-480, 2005.
    139. K. Shin and T.-J. King, "Dual stress capping layer enhancement study for hybrid orientation FinFET CMOS technology," presented at the IEEE International Electron Devices Meeting (Washington D.C., USA), December 2005.
    140. E. P. Quevy, A. San Paulo, E. Basol, R. T. Howe, T.-J. King, and J. Bokor, "Back-end-of-line Poly-SiGe disk resonators," presented at the 19th IEEE Conference on Micro Electro Mechanical Systems (Istanbul, Turkey), January 2006.
    141. E. P. Quevy, R. T. Howe, and T.-J. King, "Reconstituted wafer technology for heterogeneous integration," presented at the 19th IEEE Conference on Micro Electro Mechanical Systems (Istanbul, Turkey), January 2006.
    142. B. C.-Y. Lin, T.-J. King, and Richard S. Muller, "Poly-SiGe MEMS actuators for adaptive optics," Photonics WEST, sponsored by SPIE, The International Society for Optical Engineering, Conference 6113, Paper 6113-28, San Jose, CA, January 25, 2006.
    143. K. Shiraishi, H. Takeuchi, Y. Akasaka, H. Watanabe, N. Umezawa, T. Chikyow, Y. Nara, T.-J. K. Liu, and K. Yamada,"Mechanism of Fermi-Level Pinning for n-like Metal Silicides on Hf-based Gate Dielectrics," Proceedings of the IEEE 2006 Silicon Nanoelectronics Workshop, pp. 115-116, 2006.
    144. V. Varadarajan, L. Smith, S. Balasubramanian, and T.-J. K. Liu, "Multi-gate FET design for tolerance to statistical dopant fluctuations," Proceedings of the IEEE 2006 Silicon Nanoelectronics Workshop, pp. 137-138, 2006.
    145. Y. Yasuda, C.-H. Lin, T.-J. K. Liu, and C. Hu, "Impact of HfSiON induced flicker noise on scaling of future mixed-signal CMOS, 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 130-131, 2006.
    146. W. Xiong, K. Shin, C. R. Cleavelin, T. Schulz, K. Schruefer, I. Cayrefourcq, M. Kennard, C. Mazure, P. Paturno, and T.-J. K. Liu, "FinFET performance enhancment with tensile metal gates and strained silicon on insulator (sSOI) substrate," 2006 Device Research Conference Digest, pp. 39-40, 2006.
    147. V. Vidya and T.-J. K. Liu, "VT adjustment by Leff engineering for LSTP single gate work-function CMOS FinFET technology," presented at the 16th Biennial University Government Industry Microelectronics Symposium (San Jose, California, USA), June 2006.
    148. K. Shiraishi, H. Takeuchi, Y. Akasaka, H. Watanabe, N. Umezawa, T. Chikyow, Y. Nara, T.-J. K. Liu, and K. Yamada,"Theory of Fermi level pinning of high-k dielectrics," presented at the 2006 International Conference on Simulation of Semiconductor Proceses and Devices (Monterey, California, USA), September 2006.
    149. G. Liu, T.-J. K. Liu, and A. M. Niknejad, "A 1.2V, 2.4GHz fully integrated linear CMOS power amplifier with efficiency enhancement," presented at the 2006 IEEE Custom Integrated Circuits Conference (San Jose, California, USA), September 2006.
    150. A. Carlson, Z. Guo, S. Balasubramanian, L.-T. Pang, T.-J. K. Liu, and B. Nikolic, "FinFET SRAM with enhanced read/write margins,"  IEEE International SOI Conference Digest, pp. 105-106, 2006.
    151. C. W. Low, T.-J. K. Liu, and R. T. Howe, "Study of poly-SiGe structural properties for modularly integrated MEMS," presented at the Second International Symposium on SiGe and Ge: Materials, Processing, and Devices (Cancun, Mexico), November 2006.
    152. V. Varadarajan, Y. Yasuda, S. Balasubramanian, and T.-J. K. Liu, "WireFET technology for 3-D integrated circuits," presented at the 2006 International Electron Devices Meeting (San Francisco, California, USA), December 2006.
    153. C.-H. Hsu, W. Xiong, C.-T. Lin, Y.-T. Huang, M. Ma, C. R. Cleavelin, P. Patruno, M. Kennard, I. Cayrefourcq, K. Shin, and T.-J. K. Liu, "Multi-gate MOSFETs with dual contact etch stop liner stressors on tensile metal gate and strained silicon on insulator (SOI),"  presented at the International Symposium on VLSI Technology, Systems, and Applications (Hsinchu, Taiwan R.O.C.), April 2007.
    154. A. Padilla and T.-J. K. Liu, "Dual-bit SONOS FinFET non-volatile memory cell and new method of charge detection," presented at the International Symposium on VLSI Technology, Systems, and Applications (Hsinchu, Taiwan R.O.C.), April 2007.
    155. Best Student Paper Award: D. T. Lee, X. Sun, E. Quevy, R. T. Howe, and T.-J. K. Liu, "WetFET -- a novel fluidic gate-dielectric transistor for sensor applications," presented at the International Symposium on VLSI Technology, Systems, and Applications (Hsinchu, Taiwan R.O.C.), April 2007.
    156. P. Kalra, P. Majhi, D. Heh, G. Bersuker, C. Young, N. Vora, R. Harris, P. Kirsch, R. Choi, M. Chang, J. Lee, H. Hwang, H.-H. Tseng, R. Jammy, and T.-J. K. Liu, "Impact of flash annealing on performance and reliability of high-k/metal-gate MOSFETs for sub-45nm CMOS," International Electron Devices Meeting Technical Digest, pp. 353-356, 2007.
    157. W. Y. Choi, H. Kam, D. Lee, J. Lai, and T.-J. K. Liu, "Compact nano-electro-mechanical non-volatile memory (NEMory) for 3D integration," International Electron Devices Meeting Technical Digest, pp. 603-606, 2007.
    158. A. Carlson and T.-J. K. Liu, "Negative and iterated spacer lithography processes for low variability and ultra-dense integration," Proc. SPIE Vol. 6924, 2008.
    159. K. Patel, T.-J. K. Liu, and C. Spanos, "Impact of line edge roughness on double-gate FinFET performance variability," Proc. SPIE Vol. 6925, 2008.
    160. P. Kalra, P. Majhi, H.-H. Tseng, R. Jammy, and T.-J. K. Liu, "Optimization of flash annealing parameters to achieve ultra-shallow junctions for sub-45nm CMOS," presented at the MRS 2008 Spring Meeting (San Francisco, CA, USA), March 2008.
    161. J. Rosenbaum, P. Atkinson, T.-J. K. Liu, H. Kam, and B. Graves, "A case study on an innovative approach to on-line technical education in an industrial setting," presented at the IACEE 11th World Conference on Continuing Engineering Education (Atlanta, Georgia, USA), 2008.
    162. P. Kalra, P. Majhi, H.-H. Tseng, R. Jammy, and T.-J. K. Liu, "Infusion doping for sub-45nm CMOS technology nodes," presented at the 17th International Conference on Ion Implantation Technology (Monterey, California, USA), June 2008.
    163. C. Shin, A. Carlson, X. Sun, K. Jeon, and T.-J. K. Liu, "Tri-gate bulk MOSFET design for improved robustness to random dopant fluctuations," IEEE 2008 Silicon Nanoelectronics Workshop (Honolulu, HI, USA), June 2008.
    164. A. Carlson, X. Sun, C. Shin, and T.-J. K. Liu, "SRAM yield and performance enhancements with tri-gate bulk MOSFETs," IEEE 2008 Silicon Nanoelectronics Workshop (Honolulu, HI, USA), June 2008.
    165. A. Padilla, S. Lee, D. Carlton, and T.-J. K. Liu, "Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method," 2008 Symposium on VLSI Technology, Digest of Technical Papers, pp. 142-143, June 2008.
    166. Z. Guo, A. Carlson, L.-T. Pang, K. Duong, T.-J. K. Liu, and B. Nikolic, "Large-scale read/write margin measurement in 45nm CMOS SRAM arrays," 2008 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 42-43, June 2008.
    167. A. Carlson, Z. Guo, L.-T. Pang, T.-J. K. Liu, and B. Nikolic, "Compensation of systematic variations through optimal biasing of SRAM wordlines," IEEE Custom Integrated Circuits Conference, pp. 411-414, 2008.
    168. J. Lai and T.-J. K. Liu, "Mechanical properties of polycrystalline silicon formed by Al-2%Si induced crystallization," presented at the 214th ECS Meeting, Symposium J2 -- Microfabricated and Nanofabricated Systems for MEMS/NEMS 8 (Honolulu, HI, USA), October 2008.
    169. F. Chen, H. Kam, D. Markovic, T.-J. K. Liu, V. Stojanovic and E. Alon, "Integrated circuit design with NEM relays," 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 750-757, 2008.
    170. A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T.-J. K. Liu, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages," IEEE International Electron Devices Meeting Technical Digest, pp. 171-174, 2008.
    171. C. W. Yeung, A. Padilla, T.-J. K. Liu, and C. Hu, "Programming characteristics of the steep turn-on/off feedback FET (FBFET)," 2009 Symposium on VLSI Technology Digest, pp. 176-177, 2009.
    172. S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, "Germanium-source tunnel field effect transistors with record high ION/IOFF," 2009 Symposium on VLSI Technology Digest, pp. 178-179, 2009.
    173. C. Shin, Y. Tsukamoto, X. Sun, and T.-J. K. Liu, "Full 3D simulation of 6T-SRAM cells for the 22nm node," presented at the 2009 International Conference on Simulation of Semiconductor Process and Devices (San Diego, CA, USA), September 2009.
    174. N. Xu, X. Sun, L. Wang, A. Neureuther, and T.-J. K. Liu, "Predictive compact modeling for strain effects in nanoscale transistors," presented at the 2009 International Conference on Simulation of Semiconductor Process and Devices (San Diego, CA, USA), September 2009.
    175. M. H. Cho, C. Shin, and T.-J. K. Liu, "Convex channel design for improved capacitorless DRAM retention time," presented at the 2009 International Conference on Simulation of Semiconductor Process and Devices (San Diego, CA, USA), September 2009.
    176. Best Paper Award and Best Student Paper Award: C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, B. Nikolic, and T.-J. K. Liu, "SRAM yield enhancement with thin-BOX FD-SOI," presented at the IEEE International SOI Conference (Foster City, California, USA), October 2009.
    177. W. Kwon and T.-J. K. Liu, "A highly scalable 4F2 DRAM cell utilizing a doubly gated vertical channel, " presented at the 2009 International Conference on Solid State Devices and Materials (Miyagi, Japan), October 2009.
    178. V. Pott, H. Kam, J. Jeon, and T.-J. K. Liu, "Improvement in mechanical contact reliability with ALD TiO5 coating," presented at the American Vacuum Society 56th International Symposium (San Jose, California, USA), November 2009.
    179. S. O. Toh, Y. Tsukamoto, Z. Guo, L. Jones, T.-J. K. Liu, and B. Nikolic, "Impact of random telegraph signals on Vmin in 45nm SRAM," presented at the 2009 IEEE International Electron Devices Meeting (Baltimore, Maryland, USA), December 2009.
    180. R. Nathanael, V. Pott, H. Kam, J. Jeon, and T.-J. K. Liu, "4-terminal relay technology for complementary logic," IEEE International Electron Devices Meeting Technical Digest, pp. 223-226, 2009.
    181. H. Kam, V. Pott, R. Nathanael, J. Jeon, E. Alon, and T.-J. K. Liu, "Design and reliability of a micro-relay technology for zero-standby-power digital logic applications," IEEE International Electron Devices Meeting Technical Digest, pp. 809-811, 2009.
    182. D. Lee, V. Pott, H. Kam, R. Nathanael, T.-J. K. Liu, "AFM characterization of adhesion force in micro-relays," 2010 IEEE 23rd International Conference on Micro Electro Mechanical Systems, pp. 232-235, 2010.
    183. Jack Raper Award for Outstanding Technology-Directions: F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T.-J. K. Liu, D. Markovic, V. Stojanovic, and E. Alon, "Demonstration of integrated micro-electro-mechanical (MEM) switch circuits for VLSI applications," 2010 International Solid State Circuits Conference (San Francisco, California, USA), pp. 150-151, 2010.
    184. J. Tsai, S. O. Toh, Z. Guo, L.-T. Pang, T.-J. K. Liu, B. Nikolic, "SRAM stability characterization using tunable ring oscillators in 45nm CMOS," 2010 International Solid State Circuits Conference (San Francisco, California, USA), pp. 354-355, 2010.
    185. B. Ho, R. Vega, and T.-J. K. Liu, "Study of Germanium epitaxial recrystallization on bulk-Si substrates," presented at the 2010 MRS Spring Meeting (San Francisco, California, USA), April 2010.
    186. Y. Tsukamoto, S. O. Toh, C. Shin, A. Mairena, T.-J. K. Liu, and B. Nikolic, "Analysis of the relationship between random telegraph signal and negative bias temperature instability," presented at the 2010 IEEE International Reliability Physics Symposium (Anaheim, California, USA), May 2010.
    187. C. H. Tsai, T.-J. K. Liu, S. H. Tsai, C. F. Chang, Y. M. Tseng, R. Liao, R. M. Huang, P. W. Liu, C. T. Tsai, C. Shin, B. Nikolic, and C. W. Liang, "Segmented tri-gate bulk CMOS technology for device variability improvement," presented at the 2010 International Symposium on VLSI Technology, Systems, and Applications (Hsinchu, Taiwan R. O. C.), May 2010.
    188. W. Kwon and T.-J. K. Liu, "Compact NAND flash memory cell design utilizing backside charge storage," presented at the 2010 Silicon Nanoelectronics Workshop (Honolulu, Hawaii, USA), June 2010.
    189. K. Jeon, W. Y. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. K. Liu, and C. Hu, "Si tunnel transistors with a novel silicided source and 46mV/dec swing," presented at the 2010 Symposium on VLSI Technology (Honolulu, Hawaii, USA), June 2010.
    190. W.-Y. Loh, K. Jeon, C. Y. Kang, J. Oh, P. Patel, C. Smith, J. Barnett, C. Park, T.-J. K. Liu, H.-H. Tseng, P. Majhi, R. Jammy, and C. Hu, "Sub-60nm Si tunnel field effect transistors with ION > 100 uA/um," presented at the 2010 European Solid-State Device Research Conference (Seville, Spain), September 2010.
    191. Best Paper Award: C. Shin, B. Nikolic, T.-J. K. Liu, C. H. Tsai, M. H. Wu, C. F. Chang, Y. R. Liu, C. Y. Kao, G. S. Lin, K. L. Chiu, C.-S. Fu, C.-T. Tsai, and C. W. Liang, "Tri-gate bulk CMOS technology for improved SRAM scalability," presented at the 2010 European Solid-State Device Research Conference (Seville, Spain), September 2010.
    192. H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C. Wang, F. Chen, H. Kam, V. Pott, T.-J. K. Liu, E. Alon, V. Stojanovic, and D. Markovic, "Analysis and demonstration of MEM-relay power gating," presented at the 2010 Custom Integrated Circuits Conference (San Jose, California, USA), September 2010.
    193. L. T.-H. Wang, N. Xu, S.-O. Toh, A. R. Neureuther, T.-J. K. Liu, and B. Nikolic, "Parameter-specific ring oscillator for process monitoring at the 45nm node,"  presented at the 2010 Custom Integrated Circuits Conference (San Jose, California, USA), September 2010.
    194. N. Xu, X. Sun, W. Xiong, C. R. Cleavelin, and T.-J. K. Liu, "MuGFET carrier mobility and velocity: impacts of fin aspect ratio, orientation and stress," IEEE International Electron Devices Meeting Technical Digest, pp. 194-197, 2010.
    195. H. Kam, E. Alon, and T.-J. K. Liu, "A predictive contact reliability model for MEM logic switches," IEEE International Electron Devices Meeting Technical Digest, pp. 399-402, 2010.
    196. N. Xu, F. Andrieu, J. Jeon, X. Sun, O. Weber, T. Poiroux, B.-Y. Nguyen, O. Faynot, and T.-J. K. Liu, "Stress-induced performance enhancement in Si ultra-thin body FD-SOI MOSFETs: impacts of scaling," Symposium on VLSI Technology Digest, pp. 162-163, 2011.
    197. S. O. Toh, T.-J. K. Liu, and B. Nikolic, "Impact of random telegraph signaling noise on SRAM stability," Symposium on VLSI Technology Digest, pp. 204-205, 2011.
    198. S. H. Kim, Z. A. Jacobson, P. Patel, C. Hu, and T.-J. K. Liu, "Tunnel FET-based pass-transistor logic for ultra-low-power applications," presented at the Annual Device Research Conference (Santa Barbara, California, USA), June 2011.
    199. H. Fariborzi, F. Chen, R. Nathanael, J. Jeon, T.-J. K. Liu, and V. Stojanovic, "Design and demonstration of micro-electro-mechanical relay multipliers," presented at the IEEE Asian Solid-State Circuits Conference (Jeju, Korea), November 2011.
    200. E. S. Park, Y. Chen, T.-J. K. Liu and V. Subramanian, "Printed micro-electromechanical switches," presented at the IEEE International Electron Devices Meeting (Washington DC, USA), 2011.
    201. B. Ho, X. Sun, N. Xu, T. Sako, K. Maekawa, M. Tomoyasu, Y. Akasaka, and T.-J. K. Liu, "Fabrication of segmented-channel MOSFETs for reduced short-channel effects," presented at the International Semiconductor Device Research Symposium (College Park, Maryland, USA), December 2011.
    202. E. S. Park, Y. Chen, T.-J. K. Liu and V. Subramanian, "Inkjet-printed microshell encapsulation: a new zero-level packaging technology," presented at the 25th IEEE International Conference on Micro Electro Mechanical Systems (Paris, France), 2011.
    203. Y. Tsukamoto, M. Yabuuchi, H. Fujiwara, K. Nii, C. Shin and T.-J. K. Liu, "Quasi-planar tri-gate (QPT) bulk CMOS technology for single-port SRAM application," presented at the 13th International Symposium on Quality Electronic Design, (Santa Clara, California, USA), March 2012.
    204. R. Nathanael, J. Jeon, I-R. Chen, Y. Chen, F. Chen, H. Kam and T.-J. K. Liu, "Multi-input/multi-output relay design for more compact and versatile implementation of digital logic with zero leakage," presented at the 19th International Symposium on VLSI Technology, Systems and Applications (Hsinchu, Taiwan, R. O. C.), April 2012.
    205. I. Chen, L. Hutin, C. Park, R. Lee, R. Nathanael, J. Yaung, J. Jeon and T.-J. K. Liu, "Scaled micro-relay structure with low strain gradient for reduced operating voltage," presented at the 221st ECS Meeting (Seattle, Washington, USA), May 2012.
    206. W. Kwon, L. Hutin, and T.-J. K. Liu, "Electro-mechanical diode performance and scaling for cross-point non-volatile memory arrays," presented at the 2012 International Memory Workshop (Milano, Italy), May 2012.
    207. S. Chopra, V. Tran, B. Wood, B. Ho, Y. Kim, C.-P. Chang, S. Kuppurao, and T.-J. K. Liu, "Epitaxial growth of Si/SiGe films on corrugated structures for segmented channel Si1-xGex/Si pMOSFETs," presented at the 6th International SiGe Technology and Device Meeting (Berkeley, California, USA), June 2012.
    208. M. H. Cho, W. Kwon, N. Xu, and T.-J. K. Liu, "Variation-aware study of BJT-based capacitorless DRAM cell scaling limit," presented at the 2012 IEEE Silicon Nanoelectronics Workshop (Honolulu, Hawaii, USA), June 2012.
    209. R. J. Mears, N. Xu, N. Damrongplasit, H. Takeuchi, R. J. Stephenson, N. W. Cody, A. Yiptong, X. Huang, M. Hytha, and T.-J. K. Liu, "Simultaneous carrier transport enhancement and variability reduction in Si MOSFETs by insertion of partial monolayers of oxygen," presented at the 2012 IEEE Silicon Nanoelectronics Workshop (Honolulu, Hawaii, USA), June 2012.
    210. B. Ho, N. Xu, B. Wood, V. Tran, S. Chopra, Y. Kim, B.-Y. Nguyen, O. Bonnin, C. Mazure, S. Kuppurao, C.-P. Chang, and T.-J. K. Liu, "Segmented-channel Si1-xGex/Si pMOSFET for improved ION and reduced variability," presented at the 2012 Symposium on VLSI Technology (Honolulu, Hawaii, USA), June 2012.
    211. N. Xu, F. Andrieu, B. Ho, B.-Y. Nguyen, O. Weber, O. Faynot, T. Poiroux, and T.-J. K. Liu, "Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) fully depleted SOI MOSFETs," presented at the 2012 Symposium on VLSI Technology (Honolulu, Hawaii, USA), June 2012.
    212. N. Xu, N. Damrongplasit, H. Takeuchi, R.J. Stephenson, N.W. Cody, A. Yiptong, X. Huang, M. Hytha, R. Mears, and T.-J. K. Liu, "MOSFET performance and scalability enhancement by insertion of oxygen layers," presented at the 2012 IEEE International Electron Devices Meeting (San Francisco, California, USA), December 2012.
    213. Y. Chen, R. Nathanael, J. Yaung, L. Hutin and T.-J. K. Liu, "Reliability of MEM relays for zero leakage logic," presented at SPIE Photonics West MOEMS-MEMS: Reliability, Packaging, Testing, and Characterization of MOEMS/MEMS and Nanodevices XII (SPIE conference proceedings Vol. 8614), Paper 8614-3, February 2013.
    214. Y.-B. Liao, M.-H. Chiang, N. Damrongplasit, T.-J. K. Liu and W.-C. Hsu, “6-T SRAM cell design with gate-all-around nanowire MOSFETs,” presented at the 2013 International Symposium on VLSI Technology, Systems and Applications (Hsinchu, Taiwan R.O.C.), April 2013.
    215. H. Fariborzi, Fred Chen, R. Nathanael, I-R. Chen, L. Hutin, R. Lee, T.-J. K. Liu and V. Stojanovic, “Relays do not leak – CMOS does,” presented at the 50th Design Automation Conference (Austin, Texas, USA), June 2013.
    216. N. Xu, M. Hytha, H. Takeuchi, X. Huang, R. J. Stephenson, N. Damrongplasit, R. J. Mears and T.-J. K. Liu, “Effectiveness of quasi-confinement technology for improving p-channel Si and Ge MOSFET performance,” presented at the 2013 Silicon Nanoelectronics Workshop (Kyoto, Japan), June 2013.
    217. N. Xu, B. Ho, P. Zheng, B. Wood, V. Tran, S. Chopra, Y. Kim, O. Bonnin, C. Mazure, C.-P. Chang and T.-J. K. Liu, “Benefits of segmented Si/SiGe p-Channel MOSFETs for analog/RF applications,” presented at the 2013 Symposium on VLSI Technology (Kyoto, Japan), June 2013.
    218. I-R. Chen Y.P. Chen, L. Hutin, V. Pott, R. Nathanael and T.-J. King Liu, “Stable Ruthenium-contact relay technology for low-power logic,” presented at the 17th International Conference on Solid-State Sensors, Actuators and Microsystems, Transducers 2013 (Barcelona, Spain), June 2013.
    219. Y. P. Chen, E. S. Park, I-R. Chen, L. Hutin, V. Subramanian and T.-J. King Liu, "Micro-relay reliability improvement by inkjet-printed microshell encapsulation," presented at the 17th International Conference on Solid-State Sensors, Actuators and Microsystems, Transducers 2013 (Barcelona, Spain), June 2013.
    220. R. Going, T.-J. King Liu and M. C. Wu, "Rapid melt grown germanium gate photoMOSFET on a silicon waveguide," presented at the IEEE Photonics Conference (Bellevue, Washington, USA), September 2013.
    221. A. Khakifirooz, R. Sreenivasan, B.N. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E.C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S.M. Mignot, D. Lu, H. He, T. Yamashita, P. Morin, G. Tsutsui, C.-Y. Chen, V.S. Basker, T.E. Standaert, K. Cheng, T. Levin, B.Y. Nguyen, T.-J. King Liu, D. Guo, H. Bu, K. Rim and B. Doris "Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs," presented at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (Monterey, California, USA), October 2013.
    222. L. Hutin, W. Kwon and T.-J. King Liu, "Non-volatile electro-mechanical memory (NEMory) cell scaling for energy-efficient and high-density cross-point arrays," presented at the 3rd Berkeley Symposium on Energy Efficient Electronic Systems (Berkeley, California, USA), October 2013.
    223. N. Xuo, H. Takeuchi, N. Damrongplasit, R. J. Stephenson, M. Hytha, N. Cody, R. J. Mears and T.-J. K. Liu, “Oxygen-Inserted SegFET: A candidate for 10-nm node System-on-Chip applications,” presented at the 2014 Silicon Nanoelectronics Workshop (Honolulu, Hawaii, USA), June 2014.
    224. P. Zheng, Y.-B. Liao, N. Damrongplasit, M.-H. Chiang, W.-C. Hsu and T.-J. K. Liu,“Comparison of 10 nm GAA vs. FinFET 6-T SRAM performance and yield,” presented at the 2014 Silicon Nanoelectronics Workshop (Honolulu, Hawaii, USA), June 2014.
    225. V. Beiu, W. Ibrahim, M. Tache and T.-J. King Liu, “On ultra-low power hybrid NEMS-CMOS,” to be presented at the 14th International Conference on Nanotechnology – IEEE NANO (Toronto, Ontario, Canada), August 2014.

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Last updated July 1, 2014