Tsu-Jae King Liu
Tsu-Jae King Liu received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1984, 1986 and 1994, respectively. She joined the Xerox Palo Alto Research Center as a Member of Research Staff in 1992, to research and develop high-performance thin-film transistor technologies for flat-panel display and imaging applications. In 1996 she joined the faculty of the University of California, at Berkeley, where she is now the Conexant Systems Distinguished Professor and Chair of the Electrical Engineering and Computer Sciences (EECS) Department. From 2000 to 2004 and from 2006 to 2008, she served as the Faculty Director of the UC Berkeley Microfabrication Laboratory. From July 2004 through June 2006 she was Senior Director of Engineering in the Advanced Technology Group of Synopsys, Inc. (Mountain View, CA). From 2008 through 2012, Professor Liu was the Associate Dean for Research in the College of Engineering at UC Berkeley. She also served as Faculty Director of the UC Berkeley Marvell Nanofabrication Laboratory in 2012. Since 2012 she has been serving as Chair of the Electrical Engineering Division in the EECS Department.
Professor Liu's awards include the Ross M. Tucker AIME Electronics Materials Award (1992) for seminal work in polycrystalline silicon-germanium thin films; an NSF CAREER Award (1998) for research in thin-film transistor technology; the DARPA Significant Technical Achievement Award (2000) for development of the FinFET; the Electrical Engineering Award for Outstanding Teaching at UC Berkeley (2003); the IEEE Kiyo Tomiyasu Award (2010) for contributions to nanoscale MOS transistors, memory devices, and MEMS devices; the UC Berkeley Faculty Mentor Award (2010); the Electrochemical Society Dielectric Science and Technology Division Thomas D. Callinan Award (2011) for excellence in dielectrics and insulation investigations; the Intel Outstanding Researcher in Nanotechnology Award (2012); and the SIA University Researcher Award (2014). Her research activities are presently in nanometer-scale logic and memory devices for energy-efficient electronics. She has authored or co-authored over 450 publications and holds over 90 patents.
Professor Liu is a Fellow of the IEEE, and a past member of The Electrochemical Society (ECS), the Society for Information Display (SID), and the Materials Research Society (MRS).
- C. Qian, A. Peschot, D. Connelly, and T. King Liu, "Energy-Delay Performance Optimization of NEM Logic Relay," in IEEE Int. Electron Devices Meeting Tech. Dig. (IEDM), 2015.
- C. Qian, A. Peschot, I. Chen, Y. Chen, N. Xu, and T. King Liu, "Effect of Body Biasing on the Energy-Delay Performance of Logic Relays," IEEE Electron Device Lett., vol. 36, no. 8, pp. 862, Aug. 2015.
- Y. Chen, R. Nathanael, J. Jeon, J. Yaung, L. Hutin, and T. King Liu, "Characterization of Contact Resistance Stability in MEM Relays With Tungsten Electrodes," Journal of Microelectromechanical Systems, vol. 21, no. 3, pp. 511-513, June 2012.
- S. O. Toh, Z. Guo, T. King Liu, and B. Nikolic, "Characterization of Dynamic SRAM Stability in 45 nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 46, no. 11, pp. 2702-2712, Nov. 2011.
- V. Pott, H. Kam, R. Nathanael, J. Jeon, E. Alon, and T. King Liu, "Mechanical Computing Redux: Relays for Integrated Circit Applications," Proceedings of the IEEE, vol. 98, no. 12, pp. 2076, Dec. 2010.
- H. Kam, E. Alon, and T. King Liu, "A predictive contact reliability model for MEM logic switches," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 16.4.1 -16.4.4.
- F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J. Jeon, T. King Liu, D. Markovic, V. Stojanovic, and E. Alon, "Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 150 -151.
- F. Chen, H. Kam, D. Markovic, T. King Liu, V. Stojanovic, and E. Alon, "Integrated Circuit Design with NEM Relays," in IEEE/ACM International Conference on Computer-Aided Design, 2008.
- A. Carlson, X. Sun, C. Shin, and T. King Liu, "SRAM yield and performance enhancements with tri-gate bulk MOSFETs," in Proc. IEEE 2008 Silicon Nanoelectronics Workshop, Piscataway, NJ: IEEE Press, 2008.
- Z. Guo, A. Carlson, L. Pang, K. Duong, T. King Liu, and B. Nikolic, "Large-scale read/write margin measurement in 45nm CMOS SRAM arrays," in Proc. 2008 IEEE Symp. on VLSI Circuits, Piscataway, NJ: IEEE Press, 2008, pp. 42-43.
- X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda, C. Shin, and T. King Liu, "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap," IEEE Electron Device Letters, vol. 29, no. 5, pp. 491-493, May 2008.
- X. Sun, Q. Lu, H. Takeuchi, S. Balasubramanian, and T. King Liu, "Selective enhancement of SiO2 etch rate by Ar ion implantation for improved etch depth control," Electrochemical and Solid-State Letters, vol. 10, no. 9, pp. D89-D91, 2007.
- W. Y. Choi, H. Kam, D. Lee, J. Lai, and T. King Liu, "Compact nano-electro-mechanical non-volatile memory (NEMory) for 3D integration," in 53rd IEEE Intl. Electron Devices Meeting (IEDM 2007) Technical Digest, Piscataway, NJ: IEEE Press, 2007, pp. 603-606.
- W. Y. Choi, B. G. Park, J. D. Lee, and T. King Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007.
- T. King Liu, "Segmented channel MOS transistor," U.S. Patent 7,247,887. July 2007.
- Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King Liu, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED '05, Piscataway, NJ: IEEE, 2005, pp. 2-7.
- A. E. Franke, J. M. Heck, T. King Liu, and R. T. Howe, "Polycrystalline silicon-germanium films for integrated microsystems," J. Microelectromechanical Systems, vol. 12, no. 2, pp. 160-171, April 2003.
- B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King Liu, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10nm gate length," in 2002 IEEE Intl. Electron Devices Meeting Technical Digest, Piscataway, NJ: IEEE Press, 2002, pp. 251-254.
- Y. Choi, T. King Liu, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, March 2002.
- Y. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T. King Liu, J. Bokor, and C. Hu, "Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel (Paul Rappaport Award for 2002)," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 279-286, Feb. 2002.