Precision Timed Machines (PRET)
Isaac Liu, Jan Reineke, Hiren D. Patel1 and Edward A. Lee
Center for Hybrid and Embedded Software Systems (CHESS), National Science Foundation 0720882 (CSR-EHS: PRET), National Science Foundation 1035672 (CPS: PTIDES), National Science Foundation 0931843 (ActionWebs), Multiscale Systems Center (MuSyC), Army Research Office W911NF-11-2-0038 (DDoSoS), Air Force Research Laboratory, Robert Bosch GmBH, National Instruments, Toyota and Thales
Computing requires abstraction. Any abstraction omits details of that being abstracted, but the choice of what to omit is important. We, as a community, have chosen to abstract away the temporal properties of computation. While this can be tolerated in non-real-time systems, repeatable and predictable timing are critical to real-time embedded systems. We find the ability to specify timing requirements to be just as important as specifying functionality. However, this ability to specify timing requirements is absent from most abstraction layers such as programming languages, operating systems, compilers, networks, and processor architectures. Our long-term vision with this project is to explore and reintroduce predictable and repeatable timing as a first-class property across all layers of abstraction. We start at the lowest abstraction layer - the real-time embedded processor architecture. In its current form, the PRET architecture  consists of a thread interleaved pipeline, scratchpad memories as alternatives to caches and time-triggered access to main memory. In addition, we extend the instruction set architecture with timing instructions that ensure timing repeatability of segments of program code. We implement the PRET architecture as a cycle accurate simulator that accepts C programs compiled with the SPARC GCC tool-chain. Our current focus is on exploring 1) architectural support for inter-thread communication, 2) a programmable direct memory access controller for transferring instructions and data between the main memory and scratchpad memories , and 3) dealing with input/output and network interfaces. At higher abstraction levels, we are investigating: 1) worst-case execution time analysis through program analysis, 2) C code generation from time-triggered programming models such as Giotto  and 3) dynamic scratchpad instruction and data allocation schemes memory. Upon successfully pursuing these research directions, we plan to implement the PRET architecture as a soft-core.
- Stephen A. Edwards, Edward A. Lee. The Case for the Precision Timed (PRET) Machine. Design Automation Convention, June, 2007.
- Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel, Stephen A. Edwards and Edward A. Lee, Predictable Programming on a Precision Timed Architecture, in proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), October, 2008.
- Hiren D. Patel, Ben Lickly, Bas Burgers and Edward A. Lee, A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture, Technical Report No. UCB/EECS-2008-115, September 12, 2008
1University of Waterloo
More information: http://chess.eecs.berkeley.edu/pret