Zhengya Zhang
Ph.D. Candidate
Department of EECS
University of California,
2108 Allston Way, Suite 200
Berkeley, CA 94704-1302
Tel: (510) 666-3125
Email: zyzhang [at] eecs [dot] berkeley
[dot] edu
My
research interest is in high-performance and low-power VLSI architectures of
baseband communication systems. I am currently involved with building
efficient multicarrier digital baseband systems
and low-density parity-check code (LDPC) decoders. You can find brief
abstracts of our research here
and here.
I am a member of the Digital Circuits Design Group at
Education:
Ph.D. candidate in Electrical Engineering, University of California, Berkeley
M.S. in Electrical Engineering, University of California, Berkeley
B.A.Sc. in Computer Engineering,
University of Waterloo, Canada
Papers:
[9] Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, M. J. Wainwright, "Design
of LDPC decoders for low error rate performance," submitted, March
2008.
[8] L. Dolecek, Z. Zhang, V. Anantharam, M. J. Wainwright, B. Nikolic,
"Analysis of absorbing sets and fully absorbing sets of array-based LDPC
codes," submitted, February 2008.
[7] Z. Zhang,
L. Dolecek, B. Nikolic, V. Anantharam, M. J. Wainwright, "Lowering LDPC error
floors by postprocessing," to appear, March
2008.
[6] P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolic, M. J.
Wainwright, "Error floors in LDPC Codes: fast simulation, bounds and
hardware emulation," in Proceedings of IEEE International
Symposium on Information Theory, Toronto, Canada, July 2008.
[5] Z. Zhang, R. Winoto, A. Bahai, B. Nikolic, "Peak-to-average power ratio
reduction in an FDM broadcast system," in Proceedings of
IEEE Workshop on Signal Processing Systems, Shanghai China, October 2007.
[4]
L. Dolecek, Z. Zhang, M. J. Wainwright, V. Anantharam, B. Nikolic,
"Evaluation of the low frame error rate performance of LDPC codes using
importance sampling," in Proceedings of IEEE Information
Theory Workshop, Lake Tahoe CA, September 2007.
[3] Z. Zhang, L. Dolecek, M. J. Wainwright, V. Anantharam,
B. Nikolic, “Quantization effects of low-density
parity-check decoders,” in Proceedings of IEEE International
Conference on Communications, Glasgow UK, June 2007.
[2] L. Dolecek, Z. Zhang, V. Anantharam,
M. J. Wainwright, B. Nikolic, “Analysis of
absorbing sets for array-based LDPC codes,” in Proceedings of
IEEE International Conference on Communications, Glasgow UK, June 2007.
[1] Z.
Zhang, L. Dolecek, B. Nikolic,
V. Anantharam, M. J. Wainwright, “Investigation
of error floors of structured low-density parity-check codes by hardware
emulation,” in Proceedings of IEEE
Global Communications Conference (GLOBECOM), San Francisco CA, November
2006. (Best Paper Award Finalist)
Project reports:
[5]
Q.
Zhu, Z. Zhang, A. Pinto, A. L. Sangiovanni-Vincentelli,
“On-chip
networks modeling and simulation,” December 2003.
[4] Z. Zhang, Z. Guo, “Design
of a fully differential transconductance
amplifier,”
May 2004.
[3] Z. Zhang, Z. Guo, “Active
leakage control with sleep transistors and body bias,” May 2004.
[2] P. Droz, Z. Guo, Z. Zhang, P. Monat, “Design of
high-speed chip-to-chip electrical interface,” May 2004.
[1] Z. Zhang, “Study of permutation matrices based LDPC code
constructions,”
May 2005.