Research

My research interests are in the areas of system level synthesis and verification, hardware/software co-design, logic synthesis and physical design. My recent research focuses on automated system level synthesis and design framework for heterogeneous systems.

Automated System Level Synthesis in Platform-based Design

The separation of concerns between functionality (application) and architecture platform is a technique used to facilitate design reuse at all design levels. This separation of concerns and the successive refinement of the design by mapping functionality onto architecture are the core concepts in Platform-based Design. Optimal mapping optimizes a set of objective functions while satisfying constraints on the mapped design. While logic synthesis and layout synthesis, which can be seen as special cases of optimized mapping, have been widely researched and many excellent algorithms have been made available, the mapping problem at the system level is typically solved in an ad-hoc and implicit manner based on designer experience. 

We designed a system-level synthesis flow in which the semantics and abstraction level of the design are formally determined, mapping problem is formulated, then automatic synthesis techniques are utilized. Please refer to [C4], [T1] and [T5] for more details about the formalism. We applied this method to several industrial case studies in multimedia, automotive and control domains. 

  • Multimedia (collaboration with Intel, Xilinx)
    • We did case studies on following applications and architecture platforms, while focusing on exploring different abstraction levels:
    - Map a JPEG encoder onto Intel MXP5800 Digital Media Processor [C6].
    - Map a Motion-JPEG encoder onto Xilinx Virtex II Pro platform [T2] .

  • Automotive (collaboration with General Motors)
    • We explored common semantics between the functional model (synchronous Simulink model) and the architecture model (asynchronous distributed platform), then formulated the mapping problem, which includes task and message allocation, signal packing, priority assignment as well as period assignment.
    The complete mapping formulation is too complex to be solved for industrial size problems. Therefore, we start with tackling following sub-problems, then integrate them by using heuristics.
    - Period optimization for hard real-time distributed automotive systems [C2]
    - Task allocation, signal packing and message allocation, priority assignment for automotive systems [C1]

  • Control (collaboration with United Technologies)
    • We looked at implementing control applications on distributed systems. In industrial practice, it is important to be able to build new systems by adding functionality to existing systems while keeping original parts relatively in tact. To achieve this, it is necessary to have a methodology for formally evaluating the extensibility and automatically optimizing it. We defined task extensibility in hard real-time distributed systems and designed a mathematical framework for optimizing it while meeting design requirements, such as end-to-end latency constraints and utilization constraints. This work was submitted, and we are extending it to message extensibility and more communication protocols.

MetroII: Design Environment for Heterogeneous Systems

MetroII is the next generation of the Metropolis design framework. The main features of MetroII include importing heterogeneous IPs and separation of concerns, including function/architecture separation, behavior/performance separation, and operational/denotational separation. The framework is still under development. An early overview paper is available [C3] .

SAT Sweeping with Local Observability Don’t Cares

SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural hashing, simulation, and SAT queries. Due to its robustness and efficiency, SAT sweeping provides a solid algorithm for Boolean reasoning in functional verification and logic synthesis. In previous work, SAT sweeping merges two vertices only if they are functionally equivalent. We presented a significant extension of the SAT-sweeping algorithm that exploits local observability don’tcares (ODCs) to increase the number of vertices merged. [C5]

Partition and Placement for Multiple-Voltage Design

A voltage-island architecture for systems-on-chip is an effective way to reduce active and static power. For such multiple supply designs, various layout architectures exist. We designed two algorithms to place standard cells in a circuit rows style of implementation for dual-supply digital designs using double-height level converting flip-flops. [T3]

On-Chip Networks Modeling and Simulation

We built an interconnect model library for the synthesis and design exploration of on-chip communication networks. This library provides the energy and delay estimation interface to synthesis and simulation tools. [T4]

Abstract CPU Modeling

We constructed a parameterizable micro-architectural model for out-of-order execution and superscalar CPUs in Metropolis framework. This model enables high level micro-architectural design space exploration in Metropolis.

Non-Rectilinear Global Routing

Octilinear interconnect is a promising technique to shorten wire lengths. We designed two practical heuristic Octilinear
Steiner Tree (OSMT) algorithms based on Octilinear Spanning Graphs. [J7 , C8]

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Updated: 1/9/2008