Yunsup Lee

ASPIRE Lab, University of California, Berkeley / yunsup (at) cs.berkeley.edu

About

I am a Ph.D. candidate in Computer Science at UC Berkeley advised by Krste Asanović. I am a member of the computer architecture group in the ASPIRE Lab. I am working on RISC-V, an open-source ISA, and future data-parallel architectures to make computer systems more energy-efficient and flexible to program. VLSI design is also a part of my research, since prototyping systems is the best way to prove ideas. I am also interested in parallel programming models and compilers.

CV

Profile

Name /

Yunsup Lee

Email /

yunsup (at) cs.berkeley.edu

Address /

585B Soda Hall
University of California, Berkeley
Berkeley, CA 94720

Research Interests

Computer Architecture

My primary research interest is in building energy-efficient computer systems. I like to look across the entire computing stack to spot inefficiencies.

VLSI Design

I build hardware prototypes in silicon to prototype research ideas. By doing so, I have gained insight into computer systems. Often the devil is in the details.

Compilers

I believe that we can often make computer systems more efficient by pushing the complexity into software. That's why I also hack compilers.

Parallel Programming Models

Future computer systems would be less useful if they were hard to program. I look into programming models that strike a good balance between productivity and efficiency.

Computer Vision

Computer vision systems are computationally demanding, and hence serve as a good driving application for computer architecture research.

Networking Systems

I have built high-performance networking systems in the past, and they still continue to fascinate me.

Education

University of California, Berkeley, CA

Ph.D. Candidate in Computer Science
Advisor Krste Asanović
Proposed Thesis Scalarizing Compilers and Decoupled Vector-Fetch Architectures

August 2008 - Present
In Progress

University of California, Berkeley, CA

M.S. in Computer Science
Advisor Krste Asanović
Thesis VLSI Implementations of Vector-Thread Architectures

December 2011

Korea Advanced Institute of Science and Technology, Korea

B.S. in Division of Computer Science and Electrical Engineering (Double major)
GPA 4.10/4.3 overall (Summa Cum Laude)
Won Co-Salutatorian award by President Robert B. Laughlin, Ph.D.
Ranked first place in the CS department, and second place in the EE department
Overall ranked fourth place in KAIST

March 2001 - February 2005

Honors & Awards

Best Student Poster

HotChips 2013

2013

NVIDIA Graduate Fellowship

NVIDIA

2012-2013 (link)
2013-2014 (link)

EECS Outstanding GSI Award Honorable Mention

EECS Department, UC Berkeley

2010

Outstanding GSI Award

GSI Teaching & Resource Center, UC Berkeley

2010 (link)

Korea Foundation for Advanced Studies Scholarship

KFAS

2008-2013

Co-Salutatorian Award

KAIST

2005

Global Leader Scholarship

KAIST Kim Younghan Foundation

2002-2005

International Summer School Scholarship

KAIST

2002

Research Experience

ASPIRE Lab., Parallel Computing Lab., UC Berkeley, CA

Graduate Student Researcher, Advisor: Prof. Krste Asanović

  • Main research focus is on building energy efficient data-parallel processors.
  • Built 8 chips on 28nm FDSOI, and 45nm SOI technology nodes so far.
  • Interested in pushing designs through the VLSI flow to get accurate area, cycle time, and energy numbers.
  • Building compilers to make parallel programming easier on new data-parallel processors for research as well.
  • Contributed to SEJITS, which is an idea to bridge the gap between productivity layer programmers and efficiency layer programmers using high-level scripting languages.

August 2008 - Present
In Progress

NVIDIA Research, NVIDIA, CA

Intern, Mentors: Ronny Krashinsky, James Balfour, Manager: Steve Keckler

  • My research focused on defining and implementing scalarizing compilers that efficiently map SPMD accelerator languages, such as CUDA, down to efficient vector hardware.
  • First part is the scalarization pass, which alleviates the inefficiencies of SPMD accelerator languages by automatically detecting the scalar values and operations and factoring them out of the parallel code.
  • Second part is the predication pass, which maps the complex control flow found in SPMD accelerator languages down to predication and eliminates the need of complicated hardware structures.
  • Modified and added function passes to the NVIDIA production LLVM compiler and backend compiler to statically infer thread invariant values and to predicate control flow. Also changed code generation to support shared registers, scalar instructions, vector-scalar instructions, predicate registers, and predicated instructions.

July 2011 - June 2014

Robot Intelligence Technology Lab., KAIST, Korea

Undergraduate Researcher, Advisor: Prof. Kim, John-Hwan

  • Developed a computer vision system for 3 vs 3, 5 vs 5, 11 vs 11 robot soccer systems.
  • Worked with various frame grabbers and analog/digital CCD cameras.

September 2001 - February 2005

Work Experience

PIOLINK, Inc., Korea

Hardware Engineer

  • Developed the next-generation switching platform that sustains 160 Gbps of throughput.
  • Booted kernel on a mother board that had a 16-core embedded MIPS processor alongside a 24 10Gbps port switching fabric.
  • Built an in-house FPGA regular expression accelerator, and wrote all the system software to interface with it.

December 2006 - July 2008

PIOLINK, Inc., Korea

Software Engineer

  • Key member launching the web security firewall; was heavily involved in the process of planning, developing, and launching the product.
  • Optimized the device driver and the kernel to support high bandwidth network traffic.
  • Developed a high performance pattern matching engine.
  • Developed an automated test language and runtime to support fast regression testing.

December 2004 - December 2006

Teaching Experience

CS152 Computer Architecture and Engineering, UC Berkeley, CA

Graduate Student Instructor, Instructor: Prof. Krste Asanović

  • Integrated Chisel into the teaching material

January - May 2013 (link) (rating)

CS61C Great Ideas in Computer Architecture, UC Berkeley, CA

Graduate Student Instructor, Instructors: Prof. David Patterson, Randy Katz
Nominated for EECS Outstanding GSI Award

  • Revamped the course to accommodate more recent ideas in computer architecture, such as warehouse-scale machines (map-reduce), multi-core, and SIMD

January - May 2011 (link) (rating)

CS250 VLSI Systems Design, UC Berkeley, CA

Graduate Student Instructor, Instructors: Prof. John Wawrzynek, Krste Asanović
Received Outstanding GSI Award
Received EECS Outstanding GSI Award (Honorable Mention)

  • Brought up the VLSI toolflow from scratch, and rewrote the labs and tutorials based on the MIT 6.375 materials to make the materials coherent with the new CAD tools and the standard cell library - CS250 was taught in 1997 as a design course most recently.
  • Came up with an SRAM model compiler for the Synopsys educational process, which interfaces with CACTI to get modeled cycle time, area, and energy numbers.

August - December 2010 (link) (r)
August - December 2009 (link) (r)

Daejeon Metropolitan Office of Education, Korea

Instructor

  • Taught over 30 high school students and 30 middle school students to win 2 grand prix prizes and 2 gold medals at the national olympiads.
  • This class was run by the metropolitan office to teach algorithms to gifted youths for computer programming contests.

April 2002 - July 2004

Other Activities

Student Representative

HotChips 23

  • Organized the first HotChips Poster Session

2011

Co-Founder

Management Study-Group in KAIST (MSK)

  • Hosted an university venture start-up competition; 30 teams and 50 students participated
  • Featured in the economy section of Chosun-Ilbo, one of the three major national daily newspapers

2003 - 2005

Editor of Special Editions

KAIST Times

  • Published 30 editions including the presidential election in 2002
  • The KAIST times were printed 70,000 copies biweekly

2001 - 2003

Publications

Publications

Yunsup Lee, Andrew Waterman, Rimas Avižienis, Henry Cook, Chen Sun, Vladimir Stojanovć, Krste Asanović. "A 45nm 1.3GHz 16.7 Double-Precision GFLOPS/W RISC-V Processor with Vector Accelerators". European Solid-State Circuits Conference (ESSCIRC-2014), Venice, Italy, September 2014. To Appear.
Albert Ou, Quan Nguyen, Yunsup Lee, Krste Asanović. "A Case for MVPs: Mixed-Precision Vector Processors". 2nd International Workshop on Parallelism in Mobile Platforms (PRISM-2), at the International Symposium on Computer Architecture (ISCA-2014), Minneapolis, MN, June 2014. To Appear.
Yunsup Lee, Donggyu Kim, Hokeun Kim, Michael Soliterman, Ian Juch, Andrew Gearhart, Adam Izraelevitz, Brian Zimmer, Jonathan Bachrach, Krste Asanović. "Accelerating Energy Modeling with FPGAs". SEAK: DAC Workshop on Suite of Embedded Applications and Kernels, at the Design Automation Conference (DAC-2014), San Francisco, CA, June 2014. To Appear.
Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović. "The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0". Technical Report UCB/EECS-2014-52, EECS Department, University of California, Berkeley, May 2014. PDF
Yunsup Lee, Rimas Avižienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanović. "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators". ACM Transactions on Computer Systems, 31(3), August 2013. ACM
David Sheffield, Michael Anderson, Yunsup Lee, Kurt Keutzer. "Hardware/Software Codesign for Mobile Speech Recognition". 14th Annual Conference of the International Speech Communication Association (INTERSPEECH-2013), Lyon, France, August 2013.
Andrew Waterman, Yunsup Lee, Rimas Avižienis, Henry Cook, David Patterson, Krste Asanović. "The RISC-V Instruction Set". Poster at the Symposium on High Performance Chips (HotChips-25), Stanford, CA, August 2013.
Yunsup Lee, David Sheffield, Andrew Waterman, Michael Anderson, Kurt Keutzer, Krste Asanović. "Measuring the Gap between Programmable and Fixed-Function Accelerators: A Case Study on Speech Recognition". Poster at the Symposium on High Performance Chips (HotChips-25), Stanford, CA, August 2013. Best Student Poster of HotChips 2013.
Huy Vo, Yunsup Lee, Andrew Waterman, Krste Asanović. "A Case for OS-Friendly Hardware Accelerators". 7th Annual Workshop on the Interaction between Operating System and Computer Architecture (WIVOSCA-2013), at the 40th International Symposium on Computer Architecture (ISCA-2013), Tel Aviv, Israel, June 2013.
Yunsup Lee, Ronny Krashinsky, Vinod Grover, Stephen W. Keckler, Krste Asanović. "Convergence and Scalarization for Data-Parallel Architectures". International Symposium on Code Generation and Optimization (CGO-2013), Shenzhen, China, February 2013. PDF | Talk
Brian Zimmer, Seng Oon Toh, Huy Vo, Yunsup Lee, Olivier Thomas, Krste Asanović, Borivoje Nikolić. "SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS". IEEE Transactions on Circuits and Systems II, Volume 59, Issue 12, December 2012.
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, Krste Asanović. "Chisel: Constructing Hardware in a Scala Embedded Language". Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
Andreas Klöckner, Nicolas Pinto, Yunsup Lee, Bryan Catanzaro, Paul Ivanov, Ahmed Fasih. PyCUDA and PyOpenCL: A scripting-based approach to GPU runtime code generation. Parallel Computing, Volume 38, Issue 3, March 2012.
Yunsup Lee. Efficient VLSI Implementations of Vector-Thread Architectures. M.S. Thesis, Technical Report, UCB/EECS-2011-129, EECS Department, University of California, Berkeley, December 2011.
Yunsup Lee, Rimas Avižienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanović. The Maven Vector-Thread Architecture. Poster at the Symposium on High Performance Chips (HotChips-23), Stanford, CA, August 2011.
Yunsup Lee, Rimas Avižienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanović. "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators". International Symposium on Computer Architecture (ISCA-2011), San Jose, CA, June 2011. PDF | Talk
Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA". Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 2011. PDF
Andreas Klöckner, Nicolas Pinto, Bryan Catanzaro, Yunsup Lee, Paul Ivanov, Ahmed Fasih. "GPU Scripting and Code Generation with PyCUDA". GPU Computing Gems, Volume 2. Morgan Kaufmann, 2011.
Zhangxi Tan, Andrew Waterman, Rimas Avižienis, Yunsup Lee, Henry Cook, Krste Asanović, David Patterson. "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors". Design Automation Conference (DAC-2010), Anaheim, CA, June 2010. PDF
Bryan Catanzaro, Bor-Yiing Su, Narayanan Sundaram, Yunsup Lee, Mark Murphy, Kurt Keutzer. "Efficient, High-Quality Image Contour Detection". International Conference on Computer Vision (ICCV-2009), Kyoto, Japan, October 2009. PDF
Bryan Catanzaro, Shoaib Kamil, Yunsup Lee, Krste Asanović, James Demmel, Kurt Keutzer, John Shalf, Kathy Yelick, Armando Fox. "SEJITS: Getting Productivity AND Performance With Selective Embedded JIT Specialization". First Workshop on Programming Models for Emerging Architectures (PMEA), at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT-2009), Raleigh, NC, September 2009. PDF
Also available as UCB Technical Report UCB/EECS-2010-23.
Zhangxi Tan, Andrew Waterman, Rimas Avižienis, Yunsup Lee, David Patterson, Krste Asanović. "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors". 4th Workshop on Architectural Research Prototyping (WARP-2009), at the 36th International Symposium on Computer Architecture (ISCA-2009), Austin, TX, June 2009.

Talks

Yunsup Lee. "RISC-V: An Open, Extensible ISA for the Heterogeneous Future". Invited Talk at LG, System IC Center, Seoul, South Korea, March 2014.
Yunsup Lee. "Accelerating Energy Modeling with FPGAs". ASPIRE Retreat, Lake Tahoe, January 2014.
Yunsup Lee. "RISC-V: An Open, Extensible ISA for the Heterogeneous Future". Invited Talk at Samsung, Memory Division, Hwaseong, South Korea, September 2013.
Yunsup Lee. "Towards Energy-Efficient Data-Parallel Processors". Invited Talk at Intel, Haifa, Israel, June 2013.
Yunsup Lee, Andrew Waterman. "A Retrospective on Par Lab Architecture Research". End of Par Lab Project Celebration, Berkeley, May 2013.
Yunsup Lee. "Convergence and Scalarization for Data-Parallel Architectures". International Symposium on Code Generation and Optimization (CGO-2013), Shenzhen, China, February 2013.
Yunsup Lee, David Sheffield, Huy Vo, Andrew Waterman. "Integrating the Par Lab Stack: Image Edge Detection and Speech Recognition on TFJ Auto Vectorizer/45nm RISC-V Hwacha Vector Processor". Par Lab Retreat, Lake Tahoe, January 2013.
Yunsup Lee. "Energy-Efficient Data-Parallel Processors for Mobile Devices and Supercomputers". Invited Talk at KAIST, Daejeon, South Korea, December 2012.
Yunsup Lee. "Resiliency for Extreme Energy Efficiency". Invited Talk at CEA Leti, Grenoble, France, November 2012.
Yunsup Lee. "Resiliency for Extreme Energy Efficiency". Invited Talk at STMicroelectronics, Crolles, France, November 2012.
Yunsup Lee, Andrew Waterman, Henry Cook, Rimas Avizienis. "Integrating the Par Lab Stack: GMM Training on Asp/Chiseled RISC-V". Par Lab Retreat, Santa Cruz, June 2012.
Yunsup Lee. "Decoupled Data-Parallel Accelerators". Invited Talk at Intel, Santa Clara, CA, March 2012.
Yunsup Lee. "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators". International Symposium on Computer Architecture (ISCA-2011), San Jose, CA, June 2011.
Yunsup Lee. "Maven: A Data-Parallel Architecture for Par Lab". Par Lab Retreat, Lake Tahoe, January, 2010.
Yunsup Lee, Kevin Klues, Andrew Waterman. "Integrating the Par Lab Stack: Running Damascene on SEJITS/ROS/RAMP Gold". Par Lab Retreat, Lake Tahoe, January, 2010.