I am a graduate student in Computer Science
at UC Berkeley
advised by Krste Asanović. I am a member of the computer
architecture group in the Parallel Computing Laboratory (Par Lab).
I am working on data parallel architectures to make future manycore processors more energy-efficient and flexible to program. VLSI design is also a part of my research, since prototyping systems is the best way to prove ideas. I am also interested in parallel programming models and compilers.
- Yunsup Lee
- Parallel Computing Laboratory
- Computer Science Department
- 585B Soda Hall
- University of California at Berkeley
- Berkeley, CA 94720
- email yunsup (at) cs (dot) berkeley (dot) edu
- Computer Architecture, VLSI Design, Compilers, Parallel Programming Models, Computer Vision, Network Systems
- University of California at Berkeley, CA
Ph.D. Candidate in Computer ScienceAugust 2008 - Present
Advisor Krste Asanović
Proposed Thesis Title Low-Overhead Support of Irregular Control Flow in Data-Parallel Processors with a HW/SW Co-Design Approach
- University of California at Berkeley, CA
M.S. in Computer ScienceDecember 2011
Advisor Krste Asanović
Thesis Title VLSI Implementations of Vector-Thread Architectures
- Korea Advanced Institute of Science and Technology, Korea
B.S. in Division of Computer Science and Electrical Engineering (Double major)March 2001 - February 2005
GPA 4.10/4.3 overall (Summa Cum Laude)
Granted Co-Salutatorian award by President Robert B. Laughlin, Ph.D.
Ranked first place in the CS department, and second place in the EE department
Overall ranked fourth place in KAIST
Honors and Awards
NVIDIA Graduate Fellowship, NVIDIA2012, 2013
EECS Outstanding GSI Award Honorable Mention, EECS Dept., UC Berkeley2010
Outstanding GSI Award, GSI Teaching & Resource Center, UC Berkeley2010
Korea Foundation for Advanced Studies Scholarship, KFAS2008 - 2013
Co-Salutatorian Award, KAIST2005
Global Leader Scholarship, KAIST Kim Younghan Foundation2002 - 2005
International Summer School Scholarship, KAIST2002
- Parallel Computing Lab., UC Berkeley, CA
Graduate Student Researcher, Advisor: Prof. Krste AsanovićAugust 2008 - Present
- Main research focus is on building energy efficient data-parallel processors
- Built a couple chips on 28nm FDSOI, and 45nm SOI technology nodes so far
- Interested in pushing designs through the VLSI flow to get accurate area, cycle time, and energy numbers
- Building compilers to make parallel programming easier on new data-parallel processors for research as well
- Contributed to SEJITS, which is an idea to bridge the gap between productivity layer programmers and efficiency layer programmers using high-level scripting languages
- NVIDIA Research, NVIDIA, CA
Intern, Mentor: Ronny Krashinsky, Manager: Steve KecklerJuly 2011 - Present
- My research focuses on alleviating the inefficiencies of the SIMT programming model by automatically detecting the scalar values and operations and factoring them out of the parallel code
- Modified and added function passes to the NVIDIA production LLVM compiler to statically infer thread invariant values and changed code generation to support shared registers, scalar instructions, and vector-scalar instructions
- Researching on the architecture side to efficiently execute scalarized code as well
- Robot Intelligence Technology Lab., KAIST, Korea
Undergraduate Researcher, Advisor: Prof. Kim, John-HwanSeptember 2001 - February 2005
- Developed a computer vision system for 3 vs 3, 5 vs 5, 11 vs 11 robot soccer systems
- Worked with various frame grabbers and analog/digital CCD cameras
- PIOLINK, Inc., Korea
Hardware EngineerDecember 2006 - July 2008
- Developed the next-generation platform which sustains 160 Gbps of throughput
- Booted the kernel on the mother board which had a 16-core embedded MIPS processor integrated with a 24 10Gbps port switching fabric
- Built an in-house FPGA regular expression accelerator, and wrote all the software to interface with it
Software EngineerDecember 2004 - December 2006
- Key member launching the web security firewall - was heavily involved in the process of planning, developing, and launching the product
- Optimized the device driver and the kernel to support high bandwidth network traffic
- Developed a high performance pattern matching engine
- Developed an automated test language and a runtime to support fast regression testing
CS152 Computer Architecture and Engineering, UC Berkeley, CA
Graduate Student Instructor, Instructor: Prof. Krste AsanovićJanuary 2013 - May 2013
- Integrating Chisel into the teaching material
CS61C Great Ideas in Computer Architecture, UC Berkeley, CA
Graduate Student Instructor, Instructors: Prof. David Patterson, Randy KatzJanuary - May 2011
- Nominated for EECS Outstanding GSI Award
- Revamped the course to accommodate more recent ideas in computer architecture, such as warehouse-scale machines (map-reduce), multi-core, and SIMD
CS250 VLSI Systems Design, UC Berkeley, CA
Graduate Student Instructor, Instructors: Prof. John Wawrzynek, Krste Asanović, Dr. John LazzaroAugust - December 2009
August - December 2010
- Received Outstanding GSI Award, and EECS Outstanding GSI Award (Honorable Mention)
- Brought up the VLSI toolflow from scratch, and rewrote the labs and tutorials based on the MIT 6.375 materials to make the materials coherent with the new CAD tools and the standard cell library - CS250 was taught in 1997 as a design course most recently
- Came up with an SRAM model compiler for the Synopsys educational process, which interfaces with CACTI to get modeled cycle time, area, and energy numbers
- Daejeon Metropolitan Office of Education, Korea
InstructorApril 2002 - July 2004
- Taught over 30 high school students and 30 middle school students to win 2 grand prix prizes and 2 gold medals at the national olympiads
- This class was run by the metropolitan office to teach algorithms to gifted youths for computer programming contests
- Yunsup Lee, Ronny Krashinsky, Vinod Grover, Stephen W. Keckler, and Krste Asanović. "Convergence and Scalarization for Data-Parallel Architectures". International Symposium on Code Generation and Optimization (CGO-2013), Shenzhen, China, February 2013. PDF | Talk
- Brian Zimmer, Seng Oon Toh, Huy Vo, Yunsup Lee, Olivier Thomas, and Krste Asanović, Borivoje Nikolić. "SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS". IEEE Transactions on Circuits and Systems II, Volume 59, Issue 12, December 2012.
- Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanović. "Chisel: Constructing Hardware in a Scala Embedded Language". Design Automation Conference (DAC-2012), San Francisco, CA, June 2012.
- Andreas Klöckner, Nicolas Pinto, Yunsup Lee, Bryan Catanzaro, Paul Ivanov, Ahmed Fasih. PyCUDA and PyOpenCL: A scripting-based approach to GPU runtime code generation. Parallel Computing, Volume 38, Issue 3, March 2012.
- Yunsup Lee. Efficient VLSI Implementations of Vector-Thread Architectures. M.S. Thesis, Technical Report, UCB/EECS-2011-129, EECS Department, University of California, Berkeley, December 2011.
- Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanović. The Maven Vector-Thread Architecture. Student Poster at the Symposium on High Performance Chips (HotChips-23), Stanford, CA, August 2011.
- Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanović. "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators". International Symposium on Computer Architecture (ISCA-2011), San Jose, CA, June 2011. PDF | Talk
- Andrew Waterman, Yunsup Lee, David Patterson, and Krste Asanović. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA". Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 2011. PDF
- Andreas Klöckner, Nicolas Pinto, Bryan Catanzaro, Yunsup Lee, Paul Ivanov, Ahmed Fasih. "GPU Scripting and Code Generation with PyCUDA". GPU Computing Gems, Volume 2. Morgan Kaufmann, 2011.
- Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, Krste Asanović, David Patterson. "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors". Design Automation Conference (DAC-2010), Anaheim, CA, June 2010. PDF
- Bryan Catanzaro, Bor-Yiing Su, Narayanan Sundaram, Yunsup Lee, Mark Murphy, Kurt Keutzer. "Efficient, High-Quality Image Contour Detection". International Conference on Computer Vision (ICCV), Kyoto, Japan, October 2009. PDF
Bryan Catanzaro, Shoaib Kamil, Yunsup Lee, Krste Asanović, James Demmel, Kurt Keutzer, John Shalf, Kathy Yelick, Armando Fox.
"SEJITS: Getting Productivity AND Performance With Selective Embedded JIT Specialization".
First Workshop on Programming Models for Emerging Architectures (PMEA), at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, NC, September 2009.
Also available as UCB Technical Report UCB/EECS-2010-23.
- Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, David Patterson, Krste Asanović. "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors". 4th Workshop on Architectural Research Prototyping (WARP-2009), at the 36th International Symposium on Computer Architecture (ISCA-36), Austin, TX, June 2009.
- Yunsup Lee. "Convergence and Scalarization for Data-Parallel Architectures". International Symposium on Code Generation and Optimization (CGO-2013), Shenzhen, China, February 2013.
- Yunsup Lee, David Sheffield, Huy Vo, Andrew Waterman. "Integrating the Par Lab Stack: Image Edge Detection and Speech Recognition on TFJ Auto Vectorizer/45nm RISC-V Hwacha Vector Processor". Par Lab Retreat, Lake Tahoe, January 2013.
- Yunsup Lee. "Resiliency for Extreme Energy Efficiency". Invited Talk at CEA Leti, Grenoble, France, November 2012.
- Yunsup Lee. "Resiliency for Extreme Energy Efficiency". Invited Talk at STMicroelectronics, Crolles, France, November 2012.
- Yunsup Lee, Andrew Waterman, Henry Cook, Rimas Avizienis. "Integrating the Par Lab Stack: GMM Training on Asp/Chiseled RISC-V". Par Lab Retreat, Santa Cruz, June 2012.
- Yunsup Lee. "Decoupled Data-Parallel Accelerators". Invited Talk at Intel, Santa Clara, CA, March 2012.
- Yunsup Lee. "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators". International Symposium on Computer Architecture (ISCA-2011), San Jose, CA, June 2011.
- Yunsup Lee. "Maven: A Data-Parallel Architecture for Par Lab". Par Lab Retreat, Lake Tahoe, January, 2010.
- Yunsup Lee, Kevin Klues, Andrew Waterman. "Integrating the Par Lab Stack: Running Damascene on SEJITS/ROS/RAMP Gold". Par Lab Retreat, Lake Tahoe, January, 2010.
Student Representative, HotChips 232011
- Organized the first HotChips Student Poster Session
Editor of Special Editions, KAIST Times2001 - 2003
- Published 30 editions including the presidential election in 2002
- The KAIST times were printed 70,000 copies biweekly
Co-Founder, Management Study-Group in KAIST (MSK), Founder2003 - 2005
- Raised $25,000 for an university venture start-up competition hosted by MSK - 30 teams and 50 students participated
- Featured in the economy section of Chosun-Ilbo, one of the three major national daily newspapers