About Me

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I received the B.E. degree in Electronic Science & Technology from Shanghai Jiao Tong University, Shanghai, China, in 2008. During the spring of 2007, I studied Electrical and Computer Engineering at Carnegie Mellon University as an exchange student. Currently, I am working towards the Ph.D. degree in Electrical Engineering (with an emphasis on Integrated Circuits design) at the University of California, Berkeley.

My research includes energy-efficient high-speed links, mixed-signal building blocks, analog design methodologies, and novel devices. In the summer of 2010 and 2011, I was an engineering intern at Rambus Inc., working on next-generation low-power memory interfaces.


Publications

  1. Y. Lu and E. Alon, “Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS”,IEEE Journal of Solid-State Circuits (JSSC), Dec. 2013 (link)

  2. J. Crossley, A. Puggelli, H.-P. Le, B. Yang, R. Nancollas, K. Jung, L. Kong, N. Narevsky, Y. Lu, N. Sutardja, E. J. An, A. S. Vincentelli and E. Alon, “BAG: A Designer-Oriented Integrated Framework for the Development of AMS Circuit Generators”, IEEE/ACM International Conference On Computer Aided Design (ICCAD), Nov. 2013 (link)

  3. Y. Lu, K. Jung, Y. Hidaka, and E. Alon, “Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters”, IEEE Journal of Solid-State Circuits (JSSC), Aug. 2013 (link)

  4. Y. Lu and E. Alon, “A 66Gb/s 46mW 3-Tap Decision Feedback Equalizer in 65nm CMOS”,IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013 (link)

  5. Y. Lu, K. Jung, Y. Hidaka, and E. Alon, “A 10Gb/s 10mW 2-Tap Reconfigurable Pre-Emphasis Transmitter in 65nm LP CMOS”, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012 (link)

  6. J.Ren, D. Oh, R. Kollipara, B. Tsang, Y. Lu, J. Zerbe, and Q. Lin, “System Design Considerations for a 5Gb/s Source-Synchronous Link With Common-Mode Clocking”, IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2011 (link)

  7. L. Kong, Y. Lu, and E. Alon, “A Multi-GHz Area-Efficient Comparator with Dynamic Offset Cancellation”, IEEE Custom Integrated Circuits Conference (CICC), Sept. 2011 (link)

  8. K. Jung, Y. Lu, and E. Alon, “Power Analysis and Optimization for High-speed I/O Transceivers”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2011 (link)

  9. J. Zerbe, B. Daly, L. Luo, W. Stonecypher, W. Dettloff, J. C. Eble, T. Stone, J. Ren, B. Leibowitz, M. Bucher, P. Satarzadeh, Q. Lin, Y. Lu and R. Kollipara, “A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques”, IEEE Journal of Solid-State Circuits (JSSC), April 2011 (link)

  10. Y. Lu, J. Zerbe, “Wide-range Clock Multiplier”, US Patent 20,130,002,318 (link)


Awards

2014 IEEE Solid-State Circuits Society Predoctoral Achievement Award

2013 UC Berkeley EECS Department James H. Eaton Memorial Scholarship

2013 ADI Outstanding Designer Award

2012 Best Student Paper Award of Custom Integrated Circuits Conference

2012 Intel/Analog Devices/Catalyst Foundation CICC Student Scholarship

2008-2009 UC Berkeley EECS Department Fellowship

2006 Samsung Scholarship

2005 Schneider Electric Scholarship


Contact

View Yue Lu (吕越)'s profile on LinkedIn
Address
Berkeley Wireless Research Center,
2108 Allston Way, Suite 200,
Berkeley, CA 94704
Email
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