I received the B.E. degree in Electronic Science & Technology from Shanghai Jiao Tong University, Shanghai, China, in 2008. During the spring of 2007, I studied Electrical and Computer Engineering at Carnegie Mellon University as an exchange student. Currently, I am working towards the Ph.D. degree in Electrical Engineering (with an emphasis in Integrated Circuits design) at the University of California, Berkeley.
My research includes energy-efficient high-speed links, mixed-signal building blocks, analog design methodologies, and novel devices. In the summer of 2010 and 2011, I was an engineering intern at Rambus Inc., working on next-generation low-power memory interfaces.
Y. Lu, K. Jung, Y. Hidaka, and Elad Alon, “Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters”, to appear in IEEE JSSC
Y. Lu and E. Alon, “A 66Gb/s 46mW 3-Tap Decision Feedback Equalizer in 65nm CMOS”, IEEE ISSCC, Feb. 2013
Y. Lu, K. Jung, Y. Hidaka, and E. Alon, “A 10Gb/s 10mW 2-Tap Reconfigurable Pre-Emphasis Transmitter in 65nm LP CMOS”, IEEE CICC, Sept. 2012
J.Ren, D. Oh, R. Kollipara, B. Tsang, Y. Lu, J. Zerbe, and Q. Lin, “System Design Considerations for a 5Gb/s Source-Synchronous Link With Common-Mode Clocking”, IEEE EPEPS, Oct. 2011
L. Kong, Y. Lu, and E. Alon, “A Multi-GHz Area-Efficient Comparator with Dynamic Offset Cancellation”, IEEE CICC, Sept. 2011
K. Jung, Y. Lu, and E. Alon, “Power Analysis and Optimization for High-speed I/O Transceivers”, IEEE MWSCAS, Aug. 2011
J. Zerbe, B. Daly, L. Luo, W. Stonecypher, W. Dettloff, J. C. Eble, T. Stone, J. Ren, B. Leibowitz, M. Bucher, P. Satarzadeh, Q. Lin, Y. Lu and R. Kollipara, “A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques”, IEEE JSSC, April 2011
Y. Lu, J. Zerbe, “Wide-range Clock Multiplier”, US Patent 20,130,002,318
