I'm interested in energy-efficient parallel processors and memory systems. Recently, I helped define a new instruction set, RISC-V, to facilitate computer architecture research and education at Berkeley.

My MS thesis evaluates a variable-length instruction encoding of RISC-V, called RVC.

I work on Akaros, an open-source operating system for manycore architectures. Soon, Akaros will run on RISC-V simulators and microprocessors.

I helped build RAMP Gold, an FPGA-hosted manycore emulator. [ISCA'10 DAC'10]

The Roofline Model is an insightful visual performance model for floating-point kernels.

Older Projects

DSIMD: Dynamically Exploiting DLP in SMT Processors

APLS: An Acoustic Pinger Location System

Cyberathlete Amateur League, formerly an online competitive video gaming league with ½-million registered players

FreeCell Java applet, a Duke CS108 class project

Silicon Device Parameters Calculator

Microarchitectural BS Generator