SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

20 Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
19 Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
16 Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories
12 A Dynamically Adaptable Hardware Transactional Memory
12 SD3: A Scalable Approach to Dynamic Data-Dependence Profiling
11 ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
10 Automatic Parallelization in a Binary Rewriter
9 ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
9 Task Superscalar: An Out-of-Order Task Pipeline
8 SAFER: Stuck-At-Fault Error Recovery for Memories
8 The ZCache: Decoupling Ways and Associativity
8 AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection
8 Throughput-Effective On-Chip Networks for Manycore Accelerators
8 Adaptive Flow Control for Robust Performance and Energy
7 Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies
7 Understanding the Energy Consumption of Dynamic Random Access Memories
6 Tolerating Concurrency Bugs Using Transactions as Lifeguards
6 Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
6 ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
5 Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
5 Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors
5 Fractal Coherence: Scalably Verifiable Cache Coherence
4 Hardware Support for Relaxed Concurrency Control in Transactional Memory
4 Combating Aging with the Colt Duty Cycle Equalizer
4 Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric
4 Register Cache System Not for Latency Reduction Purpose
4 A Predictive Model for Dynamic Microarchitectural Adaptivity Control
4 Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
3 Memory Latency Reduction via Thread Throttling
3 Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling
3 STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
3 Efficient Selection of Vector Instructions Using Dynamic Programming
3 Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
2 AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
2 Sampling Dead Block Prediction for Last-Level Caches
2 Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
2 Architectural Support for Fair Reader-Writer Locking
2 Erasing Core Boundaries for Robust and Configurable Performance
2 Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
2 LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
2 Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
1 InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing
1 Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
1 Adaptive and Speculative Slack Simulations of CMPs on CMPs
0 Scalable Speculative Parallelization on Commodity Clusters