SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

67 Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
56 Facelift: Hiding and slowing down aging in multicores
54 Copy or Discard execution model for speculative parallelization on multicores
48 Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
48 Dependence-aware transactional memory for increased concurrency
47 Prefetch-Aware DRAM Controllers
44 Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
42 Notary: Hardware techniques to enhance signatures
41 From SODA to scotch: The evolution of a wireless baseband processor
37 Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
35 Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
34 The StageNet fabric for constructing resilient multicore systems
31 Token flow control
30 EVAL: Utilizing processors with variation-induced timing errors
29 Toward a multicore architecture for real-time ray-tracing
26 Efficient unicast and multicast support for CMPs
23 Tradeoffs in designing accelerator architectures for visual computing
21 Power reduction of CMP communication networks via RF-interconnects
20 Token tenure: PATCHing token counting using directory-based cache coherence
20 Power to the people: Leveraging human physiological traits to control microprocessor frequency
18 A novel cache architecture with enhanced performance and security
16 Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
16 NBTI tolerant microarchitecture design in the presence of process variation
15 CPR: Composable performance regression for scalable multiprocessor models
14 A performance-correctness explicitly-decoupled architecture
14 Adaptive data compression for high-performance low-power on-chip networks
13 Low-power, high-performance analog neural branch prediction
12 Implementing high availability memory with a duplication cache
11 Strategies for mapping dataflow blocks to distributed hardware
10 Temporal instruction fetch streaming
10 SHARK: Architectural support for autonomic protection against stealth by rootkit exploits
9 Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
9 Evaluating the effects of cache redundancy on profit
8 Shapeshifter: Dynamically changing pipeline width and speed to address process variations
8 Reconfigurable energy efficient near threshold cache architectures
6 A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags
6 Testudo: Heavyweight security analysis via statistical sampling
5 A distributed processor state management architecture for large-window processors
5 Verification of chip multiprocessor memory systems using a relaxed scoreboard
5 Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology
0 Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins