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| 309 | Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches |
| 239 | An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget |
| 208 | Die Stacking (3D) Microarchitecture |
| 165 | Managing Distributed, Shared L2 Caches through OS-Level Page Allocation |
| 159 | LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks |
| 144 | Fair Queuing Memory Systems |
| 131 | Architectural Support for Software Transactional Memory |
| 126 | ASR: Adaptive Selective Replication for CMP Caches |
| 120 | Leveraging Optical Technology in Future Bus-based Chip Multiprocessors |
| 106 | ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers |
| 105 | Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management |
| 91 | Distributed Microarchitectural Protocols in the TRIPS Prototype Processor |
| 90 | Reunion: Complexity-Effective Multicore Redundancy |
| 77 | In-Network Cache Coherence |
| 74 | Mitigating the Impact of Process Variations on Processor Register Files and Execution Units |
| 57 | A Predictive Performance Model for Superscalar Processors |
| 55 | Yield-Aware Cache Architectures |
| 50 | Adaptive Caches: Effective Shaping of Cache Behavior to Workloads |
| 45 | Memory Prefetching Using Adaptive Stream Detection |
| 41 | Coherence Ordering for Ring-based Chip Multiprocessors |
| 38 | NoSQ: Store-Load Communication without a Store Queue |
| 35 | Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers |
| 35 | Fire-and-Forget: Load/Store Scheduling with No Store Queue at All |
| 29 | CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs |
| 27 | Support for High-Frequency Streaming in CMPs |
| 26 | Fairness and Throughput in Switch on Event Multithreading |
| 24 | Scalable Cache Miss Handling for High Memory-Level Parallelism |
| 22 | Dataflow Predication |
| 21 | Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware |
| 20 | Merging Head and Tail Duplication for Convergent Hyperblock Formation |
| 17 | Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units |
| 16 | Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths |
| 16 | Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions |
| 15 | A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design |
| 14 | PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection |
| 13 | Authentication Control Point and Its Implications For Secure Processor Design |
| 13 | Serialization-Aware Mini-Graphs: Performance with Fewer Resources |
| 11 | Virtually Pipelined Network Memory |
| 10 | DMDC: Delayed Memory Dependence Checking through Age-Based Filtering |
| 9 | Memory Protection through Dynamic Access Control |
| 7 | Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection |
| 2 | Data-Dependency Graph Transformations for Superblock Scheduling |