SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

248 Managing Wire Delay in Large Chip-Multiprocessor Caches
229 Minos: Control Data Attack Prevention Orthogonal to Memory Model
166 RIFLE: An Architectural Framework for User-Centric Information-Flow Security
132 Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
115 Dynamically Controlled Resource Allocation in SMT Processors
107 AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants
100 Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization
95 Thermal Modeling, Characterization and Management of On-Chip Networks
87 Microarchitecture and Design Challenges for Gigascale Integration
82 Conjoined-Core Chip Multiprocessing
75 MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms
73 Adaptive History-Based Memory Schedulers
70 Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow
65 Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures
63 Memory Controller Optimizations for Web Servers
59 Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
57 Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication
55 Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
41 The Fuzzy Correlation between Code and Performance Predictability
39 Whole Execution Traces
36 Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy
32 Control Flow Optimization Via Dynamic Reconvergence Prediction
27 Automatic Synthesis of High-Speed Processor Simulators
23 A Hardware-Software Platform for Intrusion Prevention
21 Cache Refill/Access Decoupling for Vector Machines
18 Dynamically Trading Frequency for Complexity in a GALS Microprocessor
17 Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery
14 A Case for Clumsy Packet Processors
14 Optimal Superblock Scheduling Using Enumeration
6 Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems
5 Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation