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| 467 | Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation |
| 387 | A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor |
| 374 | Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction |
| 280 | Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data |
| 244 | Power-driven Design of Router Microarchitectures in On-chip Networks |
| 236 | Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors |
| 202 | Processor Acceleration Through Automated Instruction Set Customization |
| 182 | WaveScalar |
| 157 | Comparing Program Phase Detection Techniques |
| 154 | IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems |
| 150 | Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures |
| 150 | Efficient Memory Integrity Verification and Encryption for Secure Processors |
| 136 | Scalable Hardware Memory Disambiguation for High ILP Processors |
| 115 | Fast Secure Processor for Inhibiting Software Piracy and Tampering |
| 102 | Fast Path-Based Neural Branch Prediction |
| 88 | Reducing Design Complexity of the Load/Store Queue |
| 79 | The Reconfigurable Streaming Vector Processor (RSVPTM) |
| 75 | The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System |
| 61 | Optimum Power/Performance Pipeline Depth |
| 59 | TLC: Transmission Line Caches |
| 58 | Exploiting Value Locality in Physical Register Files |
| 52 | VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power |
| 51 | Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice |
| 49 | LLVA: A Low-level Virtual Instruction Set Architecture |
| 49 | Macro-op Scheduling: Relaxing Scheduling Loop Constraints |
| 46 | Using Interaction Costs for Microarchitectural Bottleneck Analysis |
| 40 | Beating in-order stalls with "flea-flicker" two-pass pipelining |
| 35 | Generational Cache Management of Code Traces in Dynamic Optimization Systems |
| 35 | Design and Implementation of High-Performance Memory Systems for Future Packet Buffers |
| 32 | Universal Mechanisms for Data-Parallel Architectures |
| 28 | Hardware Support for Control Transfers in Code Caches |
| 27 | IPStash: a Power-Efficient Memory Architecture for IP-lookup |
| 21 | Instruction Replication for Clustered Microarchitectures |
| 20 | Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors |
| 11 | Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches |
| 0 | Microarchitecture on the MOSFET Diet |