SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

35 Dark Silicon and the End of Multicore Scaling
23 Power Management of Online Data-Intensive Services
14 The Impact of Memory Subsystem Resource Sharing on Datacenter Applications
9 Prefetch-Aware Shared Resource Management for Multi-Core Systems
9 Benefits and Limitations of Tapping into Stored Energy For Datacenters
9 The Role of Optics in Future High Radix Switch Design
8 Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
8 Scalable Power Control for Many-Core Architectures Running Multi-threaded Applications
7 FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template
7 Energy-efficient Mechanisms for Managing Thread Context in Throughput Processors
6 A Case for Heterogeneous On-Chip Interconnects for CMPs
6 Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems
5 Vantage: Scalable and Efficient Fine-Grain Cache Partitioning
5 Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks
5 OUTRIDER: Efficient Memory Latency Tolerance with Decoupled Strands
5 Demand-Driven Software Race Detection using Hardware Performance Counters
5 Crafting a Usable Microkernel Processor and I/O System with Strict and Provable Information Flow Security
5 SRAM-DRAM Hybrid Memory with Applications to Efficient Register Files in Fine-Grained Multi-Threading Architectures
5 Rapid Identification of Architectural Bottlenecks via Precise Event Counting
4 Architecting On-Chip Interconnects for Stacked 3D STT-RAM Caches in CMPs
4 TLSync: Support for Multiple Fast Barriers Using On-Chip Transmission Lines
4 Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees
4 DBAR: An Efficient Routing Algorithm to Support Multiple Concurrent Applications in Networks-on-Chip
3 FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes
3 Sampling + DMR: Practical and Low-overhead Permanent Fault Detection
3 Adaptive Granularity Memory Systems: A Tradeoff between Storage Efficiency and Throughput
3 Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management
2 Virtualizing Performance Asymmetric Multi-core Systems
2 Rebound: Scalable Checkpointing for Coherent Shared Memory
2 CPPC: Correctable Parity Protected Cache
2 An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing
2 A Case for Globally Shared-Medium On-Chip Interconnect
2 SpecTLB: A Mechanism for Speculative Address Translation
1 Automatic Abstraction and Fault Tolerance in Cortical Microarchitectures
1 Bypass and Insertion Algorithms for Exclusive Last-level Caches
1 i-NVMM: A Secure Non-Volatile Main Memory System with Incremental Encryption
1 Releasing Efficient Beta Cores Early to Market
0 CRIB: Consolidated Rename, Issue, and Bypass
0 Moguls: a model to explore the memory hierarchy for bandwidth improvements
0 Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes