SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

171 Scalable high performance main memory system using phase-change memory technology
162 Architecting phase change memory as a scalable dram alternative
122 A durable and energy efficient main memory using phase change memory technology
108 An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
101 Reactive NUCA: near-optimal block placement and replication in distributed caches
70 Rigel: an architecture and scalable programming interface for a 1000-core accelerator
67 Firefly: illuminating future network-on-chip with nanophotonics
66 Temperature-constrained power control for chip multiprocessors with online model estimation
65 A case for bufferless routing in on-chip networks
62 Thread motion: fine-grained power management for multi-core systems
60 The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization
59 PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
56 Scaling the bandwidth wall: challenges in and avenues for CMP scaling
52 Hybrid cache architecture with disparate memory technologies
46 Hardware support for WCET analysis of hard real-time multicore systems
46 Architectural core salvaging in a multi-core processor for hard-error tolerance
44 Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
44 Phastlane: a rapid transit optical routing network
41 A case for an interleaving constrained shared-memory multi-processor
33 Disaggregated memory for expansion and sharing in blade servers
30 AnySP: anytime anywhere anyway signal processing
30 Application-aware deadlock-free oblivious routing
30 InvisiFence: performance-transparent memory ordering in conventional multiprocessors
28 Spatio-temporal memory streaming
28 SigRace: signature-based data race detection
26 Memory mapped ECC: low-cost error protection for last level caches
26 Achieving predictable performance through better memory controller placement in many-core CMPs
23 Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor
17 Internet-scale service infrastructure efficiency
16 Stream chaining: exploiting multiple levels of correlation in data prefetching
15 Multi-execution: multicore caching for data-similar executions
15 Performance and power of cache-based reconfigurable computing
15 A memory system design framework: creating smart memories
15 Dynamic performance tuning for speculative threads
14 ECMon: exposing cache events for monitoring
13 Boosting single-thread performance in multi-core systems through fine-grain multi-threading
12 Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
9 Indirect adaptive routing on large scale interconnection networks
8 A fault tolerant, area efficient architecture for Shor's factoring algorithm
7 End-to-end register data-flow continuous self-test
5 Flexible reference-counting-based hardware acceleration for garbage collection
4 Dynamic MIPS rate stabilization in out-of-order processors
2 Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors
2 End-to-end performance forecasting: finding bottlenecks before they happen