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| 163 | Corona: System Implications of Emerging Nanophotonic Technology |
| 153 | 3D-Stacked Memory Architectures for Multi-core Processors |
| 112 | Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems |
| 110 | Improving NAND Flash Based Disk Caches |
| 107 | Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors |
| 97 | Self-Optimizing Memory Controllers: A Reinforcement Learning Approach |
| 97 | Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments |
| 93 | DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently |
| 90 | Rerun: Exploiting Episodes for Lightweight Memory Race Recording |
| 83 | Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support |
| 82 | MIRA: A Multi-layered On-Chip Interconnect Router Architecture |
| 78 | TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory |
| 76 | Flexible Decoupled Transactional Memory Support |
| 75 | Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory |
| 69 | Trading off Cache Capacity for Reliability to Enable Low Voltage Operation |
| 59 | A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies |
| 55 | Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks |
| 52 | VEAL: Virtualized Execution Accelerator for Loops |
| 51 | Flexible Hardware Acceleration for Instruction-Grain Program Monitoring |
| 48 | Technology-Driven, Highly-Scalable Dragonfly Topology |
| 45 | Atom-Aid: Detecting and Surviving Atomicity Violations |
| 41 | Polymorphic On-Chip Networks |
| 33 | iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures |
| 31 | Online Estimation of Architectural Vulnerability Factor for Soft Errors |
| 27 | A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime |
| 22 | Intra-disk Parallelism: An Idea Whose Time Has Come |
| 19 | Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction |
| 18 | From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware |
| 17 | Achieving Out-of-Order Performance with Almost In-Order Complexity |
| 13 | ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency |
| 13 | Atomic Vector Operations on Chip Multiprocessors |
| 11 | Software-Controlled Priority Characterization of POWER5 Processor |
| 10 | Running a Quantum Circuit at the Speed of Data |
| 5 | A Two-Level Load/Store Queue Based on Execution Locality |
| 4 | Microcoded Architectures for Ion-Tap Quantum Computers |
| 4 | Counting Dependence Predictors |
| 2 | Fetch-Criticality Reduction through Control Independence |