SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

446 Power provisioning for a warehouse-sized computer
234 An effective hybrid transactional memory system with strong isolation guarantees
163 Express virtual channels: towards the ideal interconnection fabric
160 Adaptive insertion policies for high performance caching
144 Performance pathologies in hardware transactional memory
128 Raksha: a flexible information flow architecture for software security
125 Core fusion: accommodating software diversity in chip multiprocessors
119 BulkSC: bulk enforcement of sequential consistency
113 Making the fast case common and the uncommon case simple in unbounded transactional memory
109 Virtual hierarchies to support server consolidation
105 Anton, a special-purpose machine for molecular dynamics simulation
104 A novel dimensionally-decomposed router for on-chip communication in 3D architectures
103 Carbon: architectural support for fine-grained parallelism on chip multiprocessors
98 Virtual private caches
97 Flattened butterfly: a cost-efficient topology for high-radix networks
94 Configurable isolation: building high availability systems with commodity multi-core processors
94 An integrated hardware-software approach to flexible transactional memory
79 Comparing memory systems for chip multiprocessors
74 ReCycle: : pipeline adaptation to tolerate process variation
71 MetaTM//TxLinux: transactional memory for an operating system
71 Interconnect design considerations for large NUCA caches
60 New cache designs for thwarting software cache-based side channel attacks
57 Limiting the power consumption of main memory
57 Dynamic prediction of architectural vulnerability from microarchitectural state
54 Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures
53 A 64-bit stream processor architecture for scientific applications
51 Hardware atomicity for reliable software speculation
43 Rotary router: an efficient architecture for CMP interconnection networks
43 Mechanisms for store-wait-free multiprocessors
34 Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
33 Examining ACE analysis reliability estimates using fault-injection
32 Automated design of application specific superscalar processors: an analytical approach
31 ParallAX: an architecture for real-time physics
27 Mechanisms for bounding vulnerabilities of processor structures
27 Late-binding: enabling unordered load-store queues
26 Power model validation through thermal measurements
24 Transparent control independence (TCI)
22 Thermal modeling and management of DRAM memory systems
21 Matrix scheduler reloaded
16 Ginger: control independence using tag rewriting
15 VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
9 Performance and security lessons learned from virtualizing the alpha processor
9 Aquacore: a programmable architecture for microfluidics
5 Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits
4 Architectural implications of brick and mortar silicon manufacturing
0 Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite