SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

270 Cooperative Caching for Chip Multiprocessors
256 Techniques for Multicore Thermal Management: Classification and New Exploration
212 Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
196 Bulk Disambiguation of Speculative Threads in Multiprocessors
190 Ensemble-level Power Management for Dense Blade Servers
154 Architectural Semantics for Practical Transactional Memory
143 A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching
137 SODA: A Low-power Architecture For Software Radio
129 A Case for MLP-Aware Cache Replacement
100 A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
83 The BlackWidow High-Radix Clos Network
74 Interconnect-Aware Coherence Protocols for Chip Multiprocessors
70 Improving Cost, Performance, and Security of Memory Encryption and Authentication
69 TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
64 Learning-Based SMT Processor Resource Distribution via Hill-Climbing
64 Spatial Memory Streaming
44 Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors
42 Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
41 Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture
37 Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
34 Multiple Instruction Stream Processor
33 An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
31 Memory Model = Instruction Reordering + Store Atomicity
24 Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
23 Reducing Startup Time in Co-Designed Virtual Machines
23 Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
22 Area-Performance Trade-offs in Tiled Dataflow Architectures
20 Interconnection Networks for Scalable Quantum Computers
17 Conditional Memory Ordering
17 Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
16 Distributed Arithmetic on a Quantum Multicomputer