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| 337 | Virtualizing Transactional Memory |
| 307 | Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling |
| 262 | Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors |
| 213 | Optimizing Replication, Communication, and Capacity Allocation in CMPs |
| 202 | BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging |
| 199 | A High Throughput String Matching Architecture for Intrusion Detection and Prevention |
| 179 | The Impact of Performance Asymmetry in Emerging Multicore Architectures |
| 142 | Mitigating Amdahl's Law through EPI Throttling |
| 141 | Exploiting Structural Duplication for Lifetime Reliability Enhancement |
| 119 | Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions |
| 118 | An Ultra Low Power System Architecture for Sensor Network Applications |
| 110 | An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors |
| 109 | Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks |
| 108 | RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence |
| 107 | Computing Architectural Vulnerability Factors for Address-Based Structures |
| 104 | Architecture for Protecting Critical Secrets in Microprocessors |
| 101 | Microarchitecture of a High-Radix Router |
| 92 | Opportunistic Transient-Fault Detection |
| 92 | The V-Way Cache: Demand Based Associativity via Global Replacement |
| 85 | Design and Evaluation of Hybrid Fault-Detection Systems |
| 76 | Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors |
| 73 | Temporal Streaming of Shared Memory |
| 72 | Direct Cache Access for High Bandwidth Network I/O |
| 69 | High Efficiency Counter Mode Security Architecture via Prediction and Precomputation |
| 65 | Analysis of the O-GEometric History Length Branch Predictor |
| 63 | Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking |
| 59 | Energy Optimization of Subthreshold-Voltage Sensor Network Processors |
| 59 | Piecewise Linear Branch Prediction |
| 59 | Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization |
| 52 | A Tree Based Router Search Engine Architecture with Single Port Memories |
| 49 | Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management |
| 42 | Rescue: A Microarchitecture for Testability and Defect Tolerance |
| 41 | A Robust Main-Memory Compression Scheme |
| 41 | An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems |
| 35 | Store Buffer Design in First-Level Multibanked Data Caches |
| 34 | Deconstructing Commodity Storage Clusters |
| 34 | Techniques for Efficient Processing in Runahead Execution Engines |
| 30 | An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures |
| 27 | Improving Program Efficiency by Packing Instructions into Registers |
| 25 | RENO - A Rename-Based Instruction Optimizer |
| 25 | Dynamic Verification of Sequential Consistency |
| 16 | Continuous Optimization |
| 7 | Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines |
| 4 | Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection |
| 2 | Scalable Load and Store Processing in Latency Tolerant Processors |