SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

538 Transactional Memory Coherence and Consistency
357 Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams
304 Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance
260 Low-Latency Virtual-Channel Routers for On-Chip Networks
206 The Case for Lifetime Reliability-Aware Microprocessors
191 Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
174 A First-Order Superscalar Processor Model
132 Evaluating the Imagine Stream Architecture
120 Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
117 The Vector-Thread Architecture
112 Adaptive Cache Compression for High-Performance Processors
111 iWatcher: Efficient Architectural Support for Software Debugging
81 Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies
76 Physical Register Inlining
73 Memory Ordering: A Value-Based Approach
53 TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
51 Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
48 Use-Based Register Caching with Decoupled Indexing
48 A Content Aware Integer Register File Organization
46 A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy
44 X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs
43 Power Awareness through Selective Dynamically Optimized Traces
42 From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation
35 Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism
32 Field-testing IMPACT EPIC research results in Itanium 2
32 Prophet/Critic Hybrid Branch Prediction
31 Exploiting Resonant Behavior to Reduce Inductive Noise
19 SMTp: An Architecture for Next-generation Scalable Multi-threading
19 A Formal Approach to Frequent Energy Adaptations for Multimedia Applications
18 Wire Delay is Not a Problem for SMT (In the Near Future)
11 Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs