SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

758 Temperature-Aware Microarchitecture
431 Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture
344 SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling
317 Phase Tracking and Prediction
304 DRPM: Dynamic Speed Control for Power Mangagement in Server Class Disks
272 Transient-Fault Recovery for Chip Multiprocessors
255 A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay
218 Token Coherence: Decoupling Performance and Correctness
207 A Highly-Configurable Cache Architecture for Embedded Systems
164 Positional Adaptation of Processors: Application to Energy Reduction
134 Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor
122 Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
103 The Jrpm System for Dynamically Parallelizing Java Programs
101 Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors
100 Guided Region Prefetching: A Cooperative Hardware/Software Approach
92 Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
90 Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
82 GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks
72 Half-Price Architecture
72 Overcoming the Limitations of Conventional Vector Processors
71 A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
70 DISE: A Programmable Macro Engine for Customizing Applications
67 Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
64 A Pipelined Memory Architecture for High Throughput Network Processors
63 Energy Efficient Co-Adaptive Instruction Fetch and Issue
56 Building Quantum Wires: The Long and the Short of It
50 Performance Analysis of the Alpha 21364-BAsed HP GS1280 Multiprocessor
49 Iimplicitly-Multithreaded Processors
45 Effective ahead Pipelining of Instruction Block Address Generation
44 Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History
41 Efficient Use of Memory Bandwidth to Improve Network Processor Throughput
37 Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
36 MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
35 Detecting Global Stride Locality in Value Streams
28 Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
22 Parallelism in the Front-End