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| 606 | Drowsy Caches: Simple Techniques for Reducing Leakage Power |
| 322 | Detailed Design and Evaluation of Redundant Multithreading Alternatives |
| 274 | Managing Multi-Configuration Hardware via Dynamic Working Set Analysis |
| 253 | Transient-Fault Recovery Using Simultaneous Multithreading |
| 245 | The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays |
| 213 | Increasing Processor Performance by Implementing Deeper Pipelines |
| 210 | SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery |
| 193 | Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors |
| 190 | A Large, Fast Instruction Window for Tolerating Cache Misses |
| 174 | ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors |
| 147 | Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor |
| 137 | The Optimum Pipeline Depth for a Microprocessor |
| 134 | Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines |
| 116 | Using a User-Level Memory Thread for Correlation Prefetching |
| 101 | A Scalable Instruction Queue Design Using Dependence Chains |
| 100 | Efficient Dynamic Scheduling Through Tag Elimination |
| 93 | An Instruction Set and Microarchitecture for Instruction Level Distributed Processing |
| 88 | Slack: Maximizing Performance Under Technological Constraints |
| 85 | Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior |
| 66 | Experiences with VI Communication for Database Storage |
| 65 | Tarantula: A Vector Extension to the Alpha Architecture |
| 62 | Going the Distance for TLB Prefetching: An Application-Driven Study |
| 44 | Queue Pair IP: A Hybrid Architecture for System Area Networks |
| 43 | Difficult-Path Branch Prediction Using Subordinate Microthreads |
| 27 | Speculative Dynamic Vectorization |
| 14 | Implementing Optimizations at Decode Time |
| 10 | Avoiding Initialization Misses to the Heap |