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| 72 | A novel architecture of the 3D stacked MRAM L2 cache for CMPs |
| 55 | Express Cube Topologies for on-Chip Interconnects |
| 50 | Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs |
| 48 | Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches |
| 46 | Adaptive Spill-Receive for robust high-performance caching in CMPs |
| 37 | Variation-aware dynamic voltage/frequency scaling |
| 36 | PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches |
| 30 | Prediction router: Yet another low latency on-chip router architecture |
| 29 | A low-radix and low-diameter 3D interconnection network design |
| 29 | Accurate microarchitecture-level fault modeling for studying hardware faults |
| 29 | Elastic-buffer flow control for on-chip networks |
| 28 | Blueshift: Designing processors for timing speculation from the ground up |
| 27 | Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy |
| 26 | In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects |
| 24 | Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems |
| 24 | Bridging the computation gap between programmable processors and hardwired accelerators |
| 24 | A first-order fine-grained multithreaded throughput model |
| 21 | MRR: Enabling fully adaptive multicast routing for CMP interconnection networks |
| 20 | Design and implementation of software-managed caches for multicores with local memory |
| 19 | CAMP: A technique to estimate per-structure power at run-time using a few simple parameters |
| 17 | Eliminating microarchitectural dependency from Architectural Vulnerability |
| 17 | Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics |
| 16 | Reconciling specialization and flexibility through compound circuits |
| 16 | iCFP: Tolerating all-level cache misses in in-order processors |
| 15 | Fast complete memory consistency verification |
| 14 | Dacota: Post-silicon validation of the memory subsystem in multi-core designs |
| 12 | Voltage emergency prediction: Using signatures to reduce operating margins |
| 10 | Criticality-based optimizations for efficient load processing |
| 7 | Architectural Contesting |
| 7 | Characterization of Direct Cache Access on multi-core systems and 10GbE |
| 5 | Practical off-chip meta-data for temporal memory streaming |
| 5 | Soft error vulnerability aware process variation mitigation |
| 5 | Hardware-software integrated approaches to defend against software cache-based side channel attacks |
| 5 | Feedback mechanisms for improving probabilistic memory prefetching |
| 0 | Lightweight predication support for out of order processors |