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| 183 | System level analysis of fast, per-core DVFS using on-chip switching regulators |
| 109 | Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems |
| 96 | Cluster-level feedback power control for performance optimization |
| 84 | Regional congestion awareness for load balance in networks-on-chip |
| 73 | CMP network-on-chip overlaid with multi-band RF-interconnect |
| 56 | FlexiTaint: A programmable accelerator for dynamic taint propagation |
| 49 | Uncovering hidden loop level parallelism in sequential applications |
| 44 | A comprehensive approach to DRAM power management |
| 40 | C-Oracle: Predictive thermal management for data centers |
| 25 | Performance and power optimization through data compression in Network-on-Chip architectures |
| 24 | Automated microprocessor stressmark generation |
| 22 | EXCES: External caching in energy saving storage systems |
| 22 | Thread-safe dynamic binary translation using transactional memory |
| 21 | Fundamental performance constraints in horizontal fusion of in-order cores |
| 21 | An OS-based alternative to full hardware coherence on tiled CMPs |
| 21 | DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors |
| 21 | Runtime validation of memory ordering using constraint graph checking |
| 15 | Design and implementation of the blue gene/P snoop filter |
| 15 | Runahead Threads to improve SMT performance |
| 15 | High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation |
| 12 | Supporting highly-decoupled thread-level redundancy for parallel programs |
| 11 | Address-branch correlation: A novel locality for long-latency hard-to-predict branches |
| 11 | Roughness of microarchitectural design topologies and its implications for optimization |
| 9 | Power-Efficient DRAM Speculation |
| 9 | Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation |
| 8 | PEEP: Exploiting predictability of memory dependences in SMT processors |
| 8 | Single-level integrity and confidentiality protection for distributed shared memory multiprocessors |
| 7 | Serializing instructions in system-intensive workloads: Amdahl's Law strikes again |
| 7 | Speculative instruction validation for performance-reliability trade-off |
| 6 | Prediction of CPU idle-busy activity pattern |
| 5 | Performance-aware speculation control using wrong path usefulness prediction |
| 5 | PaCo: Probability-based path confidence prediction |
| 3 | Fabric convergence implications on systems architecture |
| 1 | Branch-mispredict level parallelism (BLP) for control independence |