|
|
| 480 | LogTM: log-based transactional memory |
| 113 | CMP design space exploration subject to physical constraints |
| 111 | Dynamic power-performance adaptation of parallel computation on chip multiprocessors |
| 99 | The common case transactional behavior of multithreaded programs |
| 79 | BulletProof: a defect-tolerant CMP switch architecture |
| 78 | Construction and use of linear regression models for processor performance analysis |
| 75 | Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads |
| 67 | Phase characterization for power: evaluating control-flow-based and event-counter-based techniques |
| 59 | Exploiting parallelism and structure to accelerate the simulation of chip multi-processors |
| 49 | ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers |
| 46 | DMA-aware memory energy management |
| 40 | Understanding the performance-temperature interactions in disk I/O of server workloads |
| 40 | High performance file I/O for the Blue Gene/L supercomputer |
| 34 | An approach for implementing efficient superscalar CISC processors |
| 31 | CORD: cost-effective (and nearly overhead-free) order-recording and data race detection |
| 26 | Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors |
| 23 | A decoupled KILO-instruction processor |
| 21 | InfoShield: a security architecture for protecting information usage in memory |
| 18 | Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM |
| 17 | Efficient instruction schedulers for SMT processors |
| 15 | Store vectors for scalable memory dependence prediction and scheduling |
| 14 | Increasing the cache efficiency by eliminating noise |
| 13 | Software-hardware cooperative memory disambiguation |
| 12 | Completely verifying memory consistency of test program executions |
| 8 | Chip-multiprocessing and beyond |
| 8 | Probabilistic counter updates for predictor hysteresis and stratification |
| 3 | Speculative synchronization and thread management for fine granularity threads |
| 2 | Industrial Perspectives: Platform Design Challenges with Many cores |
| 0 | New architectures for a new biology |
| 0 | Industrial Perspectives: System IO Network Evolution - Closing Requirement Gaps |
| 0 | Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth |