SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

422 Unbounded Transactional Memory
353 Power Efficient Processor Architecture and The Cell Processor
290 Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
198 The Soft Error Problem: An Architectural Perspective
143 Chip Multithreading: Opportunities and Challenges
136 Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
97 SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
84 Characterizing and Comparing Prevailing Simulation Techniques
83 Transition Phase Classification and Prediction
81 Improving Multiple-CMP Systems Using Token Coherence
80 A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks
75 Checkpointed Early Load Retirement
61 Distributing the Frontend for Temperature Reduction
54 A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
45 On the Limits of Leakage Power Reduction in Caches
45 SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
43 Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
38 A Small, Fast and Low-Power Register File by Bit-Partitioning
35 Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
35 Enterprise IT Trends and Implications for Architecture Research
33 Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
32 Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
31 An Efficient Programmable 10 Gigabit Ethernet Network Interface Card
31 A Unified Compressed Memory Hierarchy
26 Heat Stroke: Power-Density-Based Denial of Service in SMT
24 Multithreaded Value Prediction
22 Scatter-Add in Data Parallel Architectures
18 Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
18 Software Directed Issue Queue Power Reduction
13 Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
13 Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE
8 Tapping ZettaRAM for Low-Power Memory Systems
6 Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions