SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

168 Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management
142 Data Cache Prefetching Using a Global History Buffer
138 Organizing the Last Line of Defense before Hitting the Memory Wall for CMP
105 Out-of-Order Commit Processors
72 The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
63 Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
60 Program Counter Based Techniques for Dynamic Power Management
45 Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor
42 Understanding Scheduling Replay Schemes
36 Stream Register Files with Indexed Access
33 Accurate and Complexity-Effective Spatial Pattern Prediction
32 Synthesizing Representative I/O Workloads for TPC-H
32 Reducing Branch Misprediction Penalty via Selective Branch Recovery
31 Exploring Wakeup-Free Instruction Scheduling
29 Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration
23 Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization
21 Hardware Support for Prescient Instruction Prefetch
20 Low-Complexity Distributed Issue Queue
19 Reducing the Scheduling Critical Cycle Using Wakeup Prediction
18 Improving Disk Throughput in Data-Intensive Servers
18 A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors
17 Perceptron-Based Branch Confidence Estimation
14 Exploiting Prediction to Reduce Power on Buses
6 Processor Aware Anticipatory Prefetching in Loops
5 Signature Buffer: Bridging Performance Gap between Registers and Caches
3 Link-Time Path-Sensitive Memory Redundancy Elimination
2 Creating Converged Trace Schedules Using String Matching