|
|
| 252 | Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks |
| 249 | Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors |
| 175 | Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture |
| 172 | Variability in Architectural Simulations of Multi-Threaded Workloads |
| 146 | Caches and Hash Trees for Efficient Memory Integrity Verification |
| 116 | Front-End Policies for Improved Issue Efficiency in SMT Processors |
| 103 | A Statistically Rigorous Approach for Improving Simulation Methodology |
| 93 | A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns |
| 76 | Control Techniques to Eliminate Voltage Emergencies in High Performance Processors |
| 69 | Deterministic Clock Gating for Microprocessor Power Reduction |
| 60 | TCP: Tag Correlating Prefetchers |
| 58 | Memory System Behavior of Java-Based Middleware |
| 55 | Exploring the VLSI Scalability of Stream Processors |
| 54 | Dynamic Optimization of Micro-Operations |
| 51 | Reconsidering Complex Branch Predictors |
| 49 | Power-Aware Control Speculation through Selective Throttling |
| 43 | Inter-Cluster Communication Models for Clustered VLIW Processors |
| 42 | Just Say No: Benefits of Early Cache Miss Determination |
| 41 | Cost-Sensitive Cache Replacement Algorithms |
| 39 | Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors |
| 35 | Mini-Threads: Increasing TLP on Small-Scale SMT Processors |
| 27 | Slipstream Execution Mode for CMP-Based Multiprocessors |
| 23 | Catching Accurate Profiles in Hardware |
| 22 | Dynamic Data Dependence Tracking and its Application to Branch Prediction |
| 21 | Performance Enhancement Techniques for InfiniBand Architecture |
| 19 | Hierarchical Backoff Locks for Nonuniform Communication Architectures |
| 18 | Incorporating Predicate Information into Branch Predictors |
| 18 | Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems |
| 14 | Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services |
| 13 | Dynamic Data Replication: An Approach to Providing Fault-Tolerant Shared Memory Clusters |
| 4 | Active I/O Switches in System Area Networks |
| 2 | Billion Transistor Chips in Mainstream Enterprise Platforms of the Future |
| 1 | The State of State |