SC1110090807 0605040302
PPoPP1110090807 060503
ICS1110090807 0605040302
IPDPS1110090807 0605040302
ISCA1110090807 0605040302
ASPLOS11100908 060402
MICRO1110090807 0605040302
HPCA1110090807 0605040302

284 Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management
244 Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling
199 A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
160 Loose Loops Sink Chips
119 Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
108 Power Issues Related to Branch Prediction
102 Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
100 Improving Value Communication for Thread-Level Speculation
74 Thread-Spawning Schemes for Speculative Multithreading
71 Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors
60 Let's Study Whole-Program Cache Behaviour Analytically
56 Bandwidth Adaptive Snooping
55 Tuning Garbage Collection in an Embedded Java Environment
54 Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation
50 Evaluation of a Multithreaded Architecture for Cellular Computing
45 User-Level Communication in Cluster-Based Servers
34 Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation
29 The Minimax Cache: An Energy-Efficient Framework for Media Processors
25 Fine-Grain Priority Scheduling on Multi-Channel Memory Systems
24 Non-Vital Loads
24 Modeling Value Speculation
22 Recovery Oriented Computing: A New Research Agenda for a New Century
20 Quantifying Load Stream Behavior
11 CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters
10 Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs
8 Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files
7 The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches