SELECTED PUBLICATIONS
go back to Tsu-Jae's home page

• T.-J. King, M. G. Hack, and I-W. Wu, "Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors," Journal of Applied Physics, Vol. 75, No. 2, pp. 908-913, 1994.
• Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, X. Meng, R. Weiss, G. A. Davis, V. Aebi, and T.-J. King, “An ultra-low-temperature-fabricated poly-Si TFT with stacked composite ECR-PECVD gate oxide,” SID International Symposium Digest of Technical Papers, Vol. 29, pp. 887-890, 1998.
• Y.-J. Tung, J. Boyce, J. Ho, X. Huang, and T.-J. King, “A comparative study of hydrogen and deuterium plasma treatment effects on the performance and reliability of polysilicon TFTs,” presented at the 56th Annual Device Research Conference (Charlottesville, Virginia, USA), June 1998.
• S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W. Sigmon, Y.-J. Tung, and T.-J. King, “Polysilicon thin film transistors fabricated at 100^oC on a flexible plastic substrate,” International Electron Devices Meeting Technical Digest, pp. 257-260, 1998.
  
• T.-J. King, “Poly-Si TFT technologies for future flat-panel displays,” Information Display, Vol. 17, No. 4, pp. 24-26, 2001.

• T.-J. King, J. R. Pfiester, and K. C. Saraswat, "A variable-work-function polycrystalline-Si_1-xGe_x gate material for submicrometer CMOS technologies," IEEE Electron Device Letters, Vol. 12, No. 10, pp. 533-535, 1991.
• T.-J. King, J. P. McVittie, K. C. Saraswat, and J. R. Pfiester, "Electrical properties of heavily doped polycrystalline silicon-germanium films," IEEE Transactions on Electron Devices, Vol. 41, No. 2, pp. 228-232, 1994.
• T.-J. King and K. C. Saraswat, "Deposition and properties of low-pressure chemical-vapor deposited polycrystalline silicon-germanium films," Journal of the Electrochemical Society, Vol. 141, No. 8, pp. 2235-2241, 1994.
• W.-C. Lee, T.-J. King, and C. Hu, "Investigation of poly-Si_1-xGe_x for dual gate CMOS technology," IEEE Electron Device Letters, Vol. 19, No. 7, pp. 247-249, 1998.
• H. Takeuchi, W.-C. Lee, P. Ranade, and T.-J. King, “Improved PMOSFET short-channel performance using ultra-shallow Si_0.8Ge_0.2 source/drain extensions,” International Electron Devices Meeting Technical Digest, pp. 501-504, 1999.
• Q. Lu, R. Lin, P. Ranade, T.-J. King, and C. Hu, “Metal gate work function adjustment for future CMOS technology,” presented at the 2001 Symposium on VLSI Technology (Kyoto, Japan), June 2001.
• Q. Lu, H. Takeuchi, X. Meng, T.-J. King, C. Hu, K. Onishi, H.-J. Cho, and J. Lee, “Improved performance of ultra-thin HfO₂ CMOSFETs using poly-SiGe gate,” presented at the 2002 VLSI Symposium on Technology (Honolulu, Hawaii, USA), June 2002.
• P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable-Work-Function Molybdenum Gate Technology for FDSOI-CMOS," International Electron Devices Meeting Technical Digest, pp. 363-366, December 2002.
• A. Yagishita, T.-J. King, and J. Bokor, "Schottky barrier height reduction and drive current improvement in metal source/drain MOSFET with strained-Si channel," Extended Abstracts of the 2003 International Conference on Solid-State Devices and Materials, pp. 708-709.

• 2002 EDS Paul Rappaport Award: Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C. Hu, “Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel,” IEEE Electron Device Letters, Vol. 21, No. 4, pp. 161-163, 2000.
• D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, “FinFET -- a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2320-2325, 2000.
• Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, and C. Hu, “30nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D,” 58th Annual Device Research Conference Digest, pp. 23-24, 2000.
• J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime,” International Electron Devices Meeting Technical Digest, pp. 57-60, 2000.
• N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, “Quasi-planar NMOS FinFETs with sub-100nm gate lengths,” presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
• Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "Sub-20nm CMOS FinFET technologies,” International Electron Devices Meeting Technical Digest, pp. 421-424, 2001.
• Y.-K. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, T.-J. King, and J. Bokor "FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering," International Electron Devices Meeting Technical Digest, pp. 259-262, 2002.
• J. Fossum, M. M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J. An, and B. Yu, “Physical insights on design and modeling of nanoscale FinFETs,” International Electron Devices Meeting, pp. 679-283, 2003.

• Y.-C. King, T.-J. King, and C. Hu, "Charge-trap memory device fabricated by oxidation of Si_1-xGe_x," IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 696-700, 2001.
• C. Kuo, T.-J. King, and C. Hu, “A capacitorless double-gate DRAM cell,” IEEE Electron Device Letters, Vol. 23, No. 6, pp. 345-347, 2002.
• M. She, H. Takeuchi, and T.-J. King, “Silicon-nitride as a tunnel dielectric for improved SONOS-type flash memory,” IEEE Electron Device Letters, Vol. 24, No. 5, pp. 309-311, 2003.
• M. She and T.-J. King, “Improved SONOS-type flash memory using HfO₂ as trapping layer,” presented at the 19th IEEE Non-Volatile Semiconductor Memory Workshop (Monterey, California, USA), pp. 53-55, 2003.
• C. Kuo, T.-J. King, and C. Hu, “Direct tunneling RAM (DT-RAM) for high-density memory applications,” IEEE Electron Device Letters, Vol. 24, No. 7, pp. 475-477, 2003.
• M. She and T.-J. King, “Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance,” IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp. 1934-1940, 2003.
• C. Kuo, T.-J. King, and C. Hu, “A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications,” IEEE Transactions on Electron Devices, Vol. 50, No. 12, pp. 2408-2416, 2003.
• P. Xuan, M. She, J. Bokor, and T.-J. King, “FinFET SONOS Flash Memory for Embedded Applications,” International Electron Devices Meeting Technical Digest, pp. 609-612, 2003.

• J. M. Heck, Chris G. Keller, A. E. Franke, Lilac Muller, R. T. Howe, and T.-J. King, “High aspect ratio poly-silicon-germanium microstructures,” Proceedings of the 1999 International Conference on Solid-State Sensors and Actuators -- Transducers ‘99 (Sendai, Japan), pp. 328-331, 1999.
• A. E. Franke, Y. Jiao, M. T. Wu, T.-J. King, and R. T. Howe, “Post-CMOS modular integration of poly-SiGe microstructures using poly-Ge sacrificial layers,” Solid-State Sensor and Actuator Workshop Technical Digest, pp. 18-21, June 2000.
• A. E. Franke, T.-J. King, and R. T. Howe, “Integrated MEMS technologies,” MRS Bulletin, Vol. 26, No. 4, pp. 291-295, 2001.
• S. A. Bhave, B. L. Bircumshaw, W. Z. Low, Y.-S. Kim, T.-J. King, R. T. Howe, and A. P. Pisano, “Poly-SiGe: A high-Q structural material for integrated RF MEMS,” Solid-State Sensor and Actuator Workshop, Technical Digest, pp. 34-37, 2002.
• Invited Paper: T.-J. King, R. T. Howe and S. Sedky "Recent progress in modularly integrated MEMS technologies," International Electron Devices Meeting Technical Digest, pp. 199-202, 2002.
• M.-A. E. Eyoum and T.-J. King, “Low resistance silicon-germanium technology for modular integration of MEMS with electronics,” Journal of the Electrochemical Society, Vol. 151, No. 3, pp. J21-J25, 2004.

back to top