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POLY-Si
THIN-FILM TRANSISTOR TECHNOLOGY
- T.-J. King, M. G.
Hack, and I-W. Wu, "Effective density-of-states distributions for
accurate modeling of polycrystalline-silicon thin-film transistors,"
Journal of Applied Physics,
Vol. 75, No. 2, pp. 908-913, 1994.
- Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, X. Meng, R.
Weiss, G. A. Davis, V. Aebi, and T.-J. King, “An
ultra-low-temperature-fabricated poly-Si TFT with stacked composite
ECR-PECVD gate oxide,” SID
International Symposium Digest of Technical Papers, Vol. 29,
pp. 887-890, 1998.
- Y.-J. Tung, J. Boyce, J. Ho, X. Huang, and T.-J. King, “A comparative
study of hydrogen and deuterium plasma treatment effects on the
performance and reliability of polysilicon TFTs,” presented at the
56th Annual Device Research
Conference (Charlottesville, Virginia, USA), June 1998.
- S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W.
Sigmon, Y.-J. Tung, and T.-J.
King, “Polysilicon thin film transistors fabricated at
100oC on a flexible plastic substrate,” International Electron Devices Meeting
Technical Digest, pp. 257-260, 1998.
- T.-J. King, “Poly-Si TFT technologies for future flat-panel
displays,” Information
Display, Vol. 17, No. 4, pp. 24-26, 2001.
- D. Good, P. Wickboldt, and T.-J. King Liu, “Defect
passivation in poly-Si TFTs by ion implantation and pulsed laser
annealing,” IEEE Electron Device
Letters, Vol. 27, No. 10, pp. 840-842, 2006.
- J. Lai and T.-J. King
Liu, “Defect passivation by selenium ion implantation for
poly-Si thin film transistors,” IEEE
Electron Device Letters, Vol. 28, No. 8, pp. 725-727, 2007.
ADVANCED
CMOS MATERIALS AND PROCESSES
T.-J. King, J. R.
Pfiester, and K. C. Saraswat, "A variable-work-function
polycrystalline-Si1-xGex gate material for
submicrometer CMOS technologies," IEEE
Electron Device Letters, Vol. 12, No. 10, pp. 533-535, 1991.
T.-J. King, J. P.
McVittie, K. C. Saraswat, and J. R. Pfiester, "Electrical properties of
heavily doped polycrystalline silicon-germanium films," IEEE Transactions on Electron Devices,
Vol. 41, No. 2, pp. 228-232, 1994.
T.-J. King and K. C.
Saraswat, "Deposition and properties of low-pressure chemical-vapor
deposited polycrystalline silicon-germanium films," Journal of the Electrochemical Society,
Vol. 141, No. 8, pp. 2235-2241, 1994.
Best Student Paper Award: W.-C.
Lee, A. Wang, T.-J. King,
and C. Hu, “Impact of poly-Si0.8Ge0.2-gate
technology on device performance and reliability,” Proceedings of the 1997 International
Semiconductor Device Research Symposium, pp. 513-516, 1997.
B. Yu, Y.-J. Tung, S. Tang, E. Hui, T.-J. King, and C. Hu,
“Ultra-thin-body silicon-on-insulator MOSFET’s for terabit-scale
integration,” Proceedings of the 1997
International Semiconductor Device Research Symposium, pp. 623-626,
1997.
W.-C. Lee, T.-J. King,
and C. Hu, "Investigation of poly-Si1-xGex for dual
gate CMOS technology," IEEE Electron
Device Letters, Vol. 19, No. 7, pp. 247-249, 1998.
Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T.-J. King, and C. Hu,
“Dual-metal gate technology for deep-submicron CMOS transistors,” 2000 Symposium on VLSI Technology, Digest of
Technical Papers, pp. 72-73, 2000.
Q. Lu, R. Lin, P. Ranade, Y. C. Yeo, X. Meng, H. Takeuchi, T.-J. King, C. Hu, H. Luan, S.
Lee, W. Bai, C.-H. Lee, D.-L. Kwong, X. Guo, X. Wang, and T.-P. Ma,
“Molybdenum metal gate MOS technology for post-SiO2 gate
dielectrics,” International Electron
Devices Meeting Technical Digest, pp. 641-644, 2000.
Q. Lu, R. Lin, P. Ranade, T.-J. King, and C. Hu, “Metal
gate work function adjustment for future CMOS technology,” 2001 Symposium on VLSI Technology, Digest of
Technical Papers, pp. 45-46, 2001.
Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King, and C. Hu, “Effects
of high-k dielectrics on the workfunctions of metal and silicon gates,”
2001 Symposium on VLSI Technology, Digest
of Technical Papers, pp. 49-50, 2001.
Y.-K. Choi, T.-J.
King, and C. Hu, “A spacer patterning technology for nanoscale
CMOS,” IEEE Transactions on Electron
Devices, Vol. 49, No. 3, pp. 436-441, 2002.
I. Polishchuk P. Ranade, T.-J. King, and C. Hu, “Dual
work function metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Electron Device Letters, Vol. 23,
No. 4, pp. 200-202, 2002.
Q. Lu, H. Takeuchi, X. Meng, T.-J. King, C. Hu, K. Onishi,
H.-J. Cho, and J. Lee, “Improved performance of ultra-thin HfO2
CMOSFETs using poly-SiGe gate,” presented at the 2002 VLSI Symposium on Technology
(Honolulu, Hawaii, USA), June 2002.
P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King,
"Tunable-work-function Molybdenum gate technology for FDSOI-CMOS," International Electron Devices Meeting
Technical Digest, pp. 363-366, December 2002.
H. Takeuchi and T.-J.
King, “Scaling limits of hafnium-silicate films for CMOS
gate-dielectric application,” Applied
Physics Letters, Vol. 83, No. 4, pp. 788-790, July 2003.
A. Yagishita, T.-J.
King, and J. Bokor, "Schottky barrier height reduction and drive
current improvement in metal source/drain MOSFET with strained-Si
channel," Extended Abstracts of the 2003
International Conference on Solid-State Devices and Materials, pp.
708-709.
D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King, “Molybdenum gate
technology for ultra-thin-body MOSFETs and FinFETs,” IEEE Transactions on Electron Devices,
Vol. 51, No. 12, pp. 1989-1996, 2004.
H. Takeuchi, H. Y. Wong, D. Ha, and T.-J. King, “Impact of oxygen
vacancies on high-k gate dielectric engineering,” International Electron Devices Meeting
Technical Digest, pp. 829-832, 2004.
H. Y. Wong, H. Takeuchi, T.-J. King, M. Ameen, and A.
Agarwal, “Elimination of poly-Si gate depletion for sub-65nm CMOS
technologies by excimer laser annealing,” IEEE Electron Device Letters, Vol. 26,
No. 4, pp. 234-236, 2005.
X. Sun and T.-J. King Liu, "Spacer gate lithography for reduced
variability due to line edge roughness," IEEE Transactions on
Semiconductor Manufacturing, Vol. 23, No. 2, pp. 311-315, 2010.
THIN-BODY (FD-SOI and
FinFET/MuGFET) TRANSISTORS
- 2002 EDS Paul Rappaport Award:
Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C.
Hu, “Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a
SiGe/Si heterostructure channel,” IEEE Electron Device Letters, Vol.
21, No. 4, pp. 161-163, 2000.
- D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C.
Kuo, E. Anderson, T.-J.
King, J. Bokor, and C. Hu, “FinFET -- a self-aligned
double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron
Devices, Vol. 47, No. 12, pp. 2320-2325, 2000.
- Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, and C.
Hu, “30nm ultra-thin-body SOI MOSFET with selectively deposited Ge
raised S/D,” 58th Annual Device
Research Conference Digest, pp. 23-24, 2000.
- J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu,
"Complementary silicide source/drain thin-body MOSFETs for the 20nm
gate length regime,” International
Electron Devices Meeting Technical Digest, pp. 57-60, 2000.
- N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C.
Hu, “Quasi-planar NMOS FinFETs with sub-100nm gate lengths,” presented
at the 59th Annual Device Research
Conference (Notre Dame, Indiana, USA), June 2001.
- Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson,
T.-J. King, J. Bokor,
and C. Hu, "Sub-20nm CMOS FinFET technologies,” International Electron Devices Meeting
Technical Digest, pp. 421-424, 2001.
- B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C.
Tabery, C. Hu, T.-J.
King, J. Bokor, M.-R. Lin, and D. Kyser, "FinFET scaling:
towards 10nm gate length,"
International Electron Devices Meeting Technical Digest, pp.
251-254, 2002.
- P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King,
"Tunable-work-function molybdenum gate technology for
FDSOI-CMOS," International Electron
Devices Meeting Technical Digest, pp. 363-366, 2002.
- Y.-K. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S.
Balasubramanian, A. Agarwal, T.-J. King, and J. Bokor
"FinFET process refinements for improved mobility and gate work
function engineering," International
Electron Devices Meeting Technical Digest, pp. 259-262, 2002.
- Invited: L. Chang, Y.-K.
Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, “Extremely
scaled silicon nano-CMOS devices,” Proceedings of the IEEE, Vol. 91,
No. 11, pp. 1860-1873, 2003.
- Y.-K. Choi, D. Ha, J. Bokor, and T.-J. King, “Reliability
study of CMOS FinFETs,” International
Electron Devices Meeting Technical Digest, pp. 177-180, 2003.
- J. Fossum, M. M. Chowdhury, V. P. Trivedi, T.-J. King, Y.-K. Choi, J.
An, and B. Yu, “Physical insights on design and modeling of nanoscale
FinFETs,” International Electron
Devices Meeting, pp. 679-283, 2003.
- W. Xiong, G. Gebara, J. Zaman, M. Gostkowski, B. Nguyen, G. Smith,
D. Lewis, C. R. Cleavelin, R. Wise, S. Yu, M. Pas, T.-J. King, and J. P.
Colinge, “Improvement of FinFET electrical characteristics by hydrogen
annealing,” IEEE Electron Device
Letters, Vol. 25, No. 8, pp. 541-543, 2004.
- S. Balasubramanian, J. L. Garrett, V. Vidya, B. Nikolic, and T.-J. King, “Energy-delay
optimization of thin-body MOSFETs for the sub-15nm regime,” 2004 IEEE International SOI Conference
Digest, pp. 27-29, 2004.
- D. Ha, H. Takeuchi, Y.-K. Choi, T.-J. King, W. Bai, D.-L.
Kwong, A. Agarwal, and M. Ameen, “Molybdenum-gate HfO2 CMOS
FinFET technology,” International Electron Devices Meeting
Technical Digest, pp. 643-646, 2004.
- Best Paper Award: Z. Guo,
S. Balasubramanian, R. Zlatanovici, T.-J. King, and Borivoje
Nikolic, “FinFET-based SRAM design,” presented at the International Symposium on Low Power
Electronics and Design (San Diego, California, USA), pp. 2-7,
August 2005.
- V. Vidya and T.-J. King
Liu, “VT adjustment by Leff engineering
for LSTP single gate work-function CMOS FinFET technology,” presented
at the 16th Biennial University
Government Industry Microelectronics Symposium (San Jose,
California, USA), June 2006.
- W. Xiong, C. R. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K.
Schruefer, G. Gebara, K. Mathews, P. Patruno, I. Cayrefourcq, M.
Kennard, C. Mazure, K. Shin, and T.-J. King Liu, “Impact of
strained-silicon-on-insulator (sSOI) substrate on FinFET mobility,”
IEEE Electron Device Letters,
Vol. 27, No. 7, pp. 612-614, 2006.
- K. Shin, W. Xiong, C. Y. Cho, C. R. Cleavelin, T. Schulz, K.
Schruefer, P. Patruno, L. Smith, and T.-J. King Liu, “Study of
bending-induced strain effects on MuGFET performance,” IEEE Electron Device Letters, Vol.
27, No. 8, pp. 671-673, 2006.
- A. Carlson, Z. Guo, S. Balasubramanian, L.-T. Pang, T.-J. King Liu, and B.
Nikolic, “FinFET SRAM with enhanced read/write margins,” IEEE International SOI Conference
Digest, pp. 105-106, 2006.
- P. Kalra, P. Majhi, D. Heh, G. Bersuker, C. Young, N. Vora, R.
Harris, P. Kirsch, R. Choi, M. Chang, J. Lee, H. Hwang, H.-H. Tseng,
R. Jammy, and T.-J. King
Liu, “Impact of flash annealing on performance and reliability
of high-k/metal-gate MOSFETs for sub-45nm CMOS,” International Electron Devices Meeting
Technical Digest, pp. 353-356, 2007.
- R. Nathanael, W. Xiong, and T.-J. King Liu, “Impact of
gate-induced strain on MuGFET reliability,” IEEE Electron Device Letters, Vol.
29, pp. 916-919, 2008.
- V. Varadarajan and T.-J.
K. Liu, “FinFET design for tolerance to statistical dopant
fluctuations,” IEEE Transactions on
Nanotechnology, Vol. 8, No. 3, pp. 375-378, 2009.
- Invited: T.-J. King Liu, C. Shin, Z. Guo,
M. H. Cho, B. Nikolic, and B.-Y. Nguyen, "SRAM cell design
considerations for SOI technology," presented at the IEEE
International SOI Conference (Foster City, California, USA),
October 2009.
- Best Paper Award and Best Student
Paper Award: C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, B.
Nikolic, and T.-J. King
Liu, “SRAM yield enhancement with thin-BOX FD-SOI,” presented
at the IEEE International SOI
Conference (Foster City, California, USA), October 2009.
- Invited: B. Nikolic, C. Shin, M. H. Cho, X. Sun,
T.-J. King Liu, and B.-Y. Nguyen, "SRAM design in
fully-depleted SOI technology," presented at the IEEE
International Symposium on Circuits and Systems (Paris, France),
May 2010.
- C. Shin, M. H. Cho, Y. Tsukamoto, B.-Y. Nguyen, C. Mazure, B.
Nikolic, and T.-J. King Liu, "Performance and area scaling
benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node,"
IEEE Transactions on Electron Devices, Vol. 57, No. 6, pp.
1301-1309, 2010.
- N. Xu, X. Sun, W. Xiong, C. R. Cleavelin, and T.-J. King
Liu, "MuGFET carrier mobility and velocity: impacts of fin aspect
ratio, orientation and stress," presented at the 2010 IEEE
International Electron Devices Meeting (San Francisco,
California, USA), December 2010.
SEGMENTED
BULK MOSFETs
- X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S.
Ikeda, C. Shin, and T.-J.
King Liu, “Tri-gate bulk MOSFET design for CMOS scaling to the
end of the roadmap,” IEEE Electron
Device Letters, Vol. 29, no. 5, pp. 491-493, 2008.
- C. Shin, A. Carlson, X. Sun, K. Jeon, and T.-J. King Liu, “Tri-gate
bulk MOSFET design for improved robustness to random dopant
fluctuations,” IEEE 2008 Silicon
Nanoelectronics Workshop (Honolulu, HI, USA), June 2008.
- A. Carlson, X. Sun, C. Shin, and T.-J. King Liu, “SRAM yield
and performance enhancements with tri-gate bulk MOSFETs,” IEEE 2008 Silicon Nanoelectronics
Workshop (Honolulu, HI, USA), June 2008.
- C. Shin, X. Sun, and T.-J. King Liu, "Study of
random-dopant-fluctuation (RDF) effects for the tri-gate bulk MOSFET,"
IEEE Transactions on Electron
Devices, Vol. 56, No. 7, pp. 1538-1542, 2009.
- X. Sun and T.-J. King
Liu, “Scale length assessment of the tri-gate bulk MOSFET
design,” IEEE Transactions on
Electron Devices, Vol. 56, No. 11, pp. 2840-2842, 2009.
- R. Vega and T.-J. King Liu, "Low standby power bulk MOSFET
design using high-k trench isolation," IEEE Electron Device
Letters, Vol. 30, No. 12, pp. 1380-1382, 2009.
- C. H. Tsai, T.-J. King Liu, S. H. Tsai, C. F. Chang, Y. M.
Tseng, R. Liao, R. M. Huang, P. W. Liu, C. T. Tsai, C. Shin, B.
Nikolic, and C. W. Liang, "Segmented tri-gate bulk CMOS technology for
device variability improvement," presented at the 2010
International Symposium on VLSI Technology, Systems, and
Applications (Hsinchu, Taiwan R. O. C.), May 2010.
- Best Paper Award: C. Shin, B. Nikolic, T.-J.
King Liu, C. H. Tsai, M. H. Wu, C. F. Chang, Y. R. Liu, C. Y. Kao,
G. S. Lin, K. L. Chiu, C.-S. Fu, C.-T. Tsai, and C. W. Liang,
"Tri-gate bulk CMOS technology for improved SRAM scalability,"
presented at the 2010 European Solid-State Device Research
Conference (Seville, Spain), September 2010.
- R. A. Vega and T.-J. King Liu, "Comparative study of FinFET
vs. quasi-planar HTI MOSFET for ultimate scalability," IEEE
Transactions on Electron Devices, Vol. 57, No. 12, pp.
3250-3256, 2010.
STEEPLY
SWITCHING (SUB-60mV SWING) SEMICONDUCTOR DEVICES
- W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, “Tunneling
field-effect transistors (TFETs) with subthreshold swing (SS) less
than 60 mV/dec,” IEEE Electron Device
Letters, Vol. 28, No. 8, pp. 743-745, 2007.
- A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T.-J. King Liu, “Feedback
FET: A novel transistor exhibiting steep switching behavior at low
bias voltages,” IEEE International
Electron Devices Meeting Technical Digest, 2008.
- S. H. Kim, H. Kam, C. Hu, and T.-J. King Liu,
"Germanium-source tunnel field effect transistors with record high
ION/IOFF," presented at the 2009 Symposium on VLSI Technology
(Kyoto, Japan), June 2009.
- C. W. Yeung, A. Padilla, T.-J. King Liu, and C. Hu,
"Programming characteristics of the steep turn-on/off feedback FET
(FBFET)," presented at the 2009
Symposium on VLSI Technology (Kyoto, Japan), June 2009.
- K. Jeon, W. Y. Loh, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C.
Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J.
King Liu, and C. Hu, "Si tunnel transistors with a novel silicided
source and 46mV/dec swing," presented at the 2010 Symposium on
VLSI Technology (Honolulu, Hawaii, USA), June 2010.
- S. H. Kim, Z. A. Jacobson, and T.-J. King Liu, "Impact of
body doping and thickness on the performance of germanium-source
TFETs," IEEE Transactions on Electron Devices, Vol. 57,
No. 7, pp. 1710-1713, 2010.
- S. H. Kim, S. Agarwal, Z. A. Jacobson, P. Matheu, C. Hu, and
T.-J. King Liu, "Tunnel field effect transistor with raised
germanium source," IEEE Electron Device Letters, Vol. 31, No.
10, pp. 1107-1109, 2010.
- T.-J. King Liu and S. H. Kim, "Tunnel FET promise and
challenges," presented at the 2010 International Conference on
Solid-State Devices and Materials (Tokyo, Japan), September 2010.
SEMICONDUCTOR MEMORY DEVICES
- Y.-C. King, T.-J.
King, and C. Hu, "Charge-trap memory device fabricated by
oxidation of Si1-xGex," IEEE Transactions on Electron
Devices, Vol. 48, No. 4, pp. 696-700, 2001.
- C. Kuo, T.-J.
King, and C. Hu, “A capacitorless double-gate DRAM cell,” IEEE Electron Device Letters, Vol.
23, No. 6, pp. 345-347, 2002.
- M. She, H. Takeuchi, and T.-J. King, “Silicon-nitride
as a tunnel dielectric for improved SONOS-type flash memory,” IEEE Electron Device Letters, Vol.
24, No. 5, pp. 309-311, 2003.
- M. She and T.-J.
King, “Improved SONOS-type flash memory using HfO2
as trapping layer,” presented at the 19th IEEE Non-Volatile Semiconductor Memory
Workshop (Monterey, California, USA), pp. 53-55, 2003.
- C. Kuo, T.-J.
King, and C. Hu, “Direct tunneling RAM (DT-RAM) for
high-density memory applications,”
IEEE Electron Device Letters, Vol. 24, No. 7, pp. 475-477,
2003.
- M. She and T.-J.
King, “Impact of crystal size and tunnel dielectric on
semiconductor nanocrystal memory performance,” IEEE Transactions on Electron
Devices, Vol. 50, No. 9, pp. 1934-1940, 2003.
- C. Kuo, T.-J.
King, and C. Hu, “A capacitorless double gate DRAM technology
for sub-100-nm embedded and stand-alone memory applications,” IEEE Transactions on Electron
Devices, Vol. 50, No. 12, pp. 2408-2416, 2003.
- P. Xuan, M. She, J. Bokor, and T.-J. King, “FinFET SONOS
flash memory for embedded applications,” International Electron Devices Meeting
Technical Digest, pp. 609-612, 2003.
- A. Padilla, T.-J. King
Liu, J. W. Hyun, I. Yoo, and Y. Park, “Dual-bit
gate-sidewall-storage FinFET non-volatile memory cell and new method
of charge detection,” IEEE Electron
Device Letters, Vol. 28, No. 6, pp. 502-505, 2007.
- A. Padilla, S. Lee, D. Carlton, and T.-J. King Liu, “Enhanced
endurance of dual-bit SONOS NVM cells using the GIDL read method,”
2008 Symposium on VLSI Technology,
Digest of Technical Papers, pp. 142-143, June 2008.
- M. H. Cho, C. Shin, and T.-J. King Liu, “Convex
channel design for improved capacitorless DRAM retention time,”
presented at the 2009 International
Conference on Simulation of Semiconductor Process and Devices
(San Diego, CA, USA), September 2009.
- W. Kwon and T.-J. King
Liu, "A highly scalable 4F2 DRAM cell utilizing a
doubly gated vertical channel, " presented at the 2009 International Conference on Solid
State Devices and Materials (Miyagi, Japan), October 2009.
MICRO-ELECTRO-MECHANICAL SYSTEMS
(MEMS) TECHNOLOGY
- J. M. Heck, Chris G. Keller, A. E. Franke, Lilac Muller, R. T.
Howe, and T.-J. King,
“High aspect ratio poly-silicon-germanium microstructures,” Proceedings of the 1999 International
Conference on Solid-State Sensors and Actuators -- Transducers
‘99 (Sendai, Japan), pp. 328-331, 1999.
- A. E. Franke, D. Bilic, D. T. Chang, P. T. Jones, T.-J. King, R. T. Howe, and
G. C. Johnson, “Optimization of poly-silicon-germanium as a
microstructural material,” in Proceedings of the 1999 International
Conference on Solid-State Sensors and Actuators -- Transducers
‘99 (Sendai, Japan), pp. 530-533, 1999.
- A. E. Franke, Y. Jiao, M. T. Wu, T.-J. King, and R. T. Howe,
“Post-CMOS modular integration of poly-SiGe microstructures using
poly-Ge sacrificial layers,” Solid-State Sensor and Actuator Workshop
Technical Digest, pp. 18-21, June 2000.
- A. E. Franke, T.-J.
King, and R. T. Howe, “Integrated MEMS technologies,” MRS Bulletin, Vol. 26, No. 4, pp.
291-295, 2001.
- S. A. Bhave, B. L. Bircumshaw, W. Z. Low, Y.-S. Kim, T.-J. King, R. T. Howe, and
A. P. Pisano, “Poly-SiGe: A high-Q structural material for integrated
RF MEMS,” Solid-State Sensor and
Actuator Workshop, Technical Digest, pp. 34-37, 2002.
- Invited Paper: T.-J. King, R. T. Howe and
S. Sedky "Recent progress in modularly integrated MEMS technologies,"
International Electron Devices
Meeting Technical Digest, pp. 199-202, 2002.
- M.-A. E. Eyoum and T.-J.
King, “Low resistance silicon-germanium technology for modular
integration of MEMS with electronics,” Journal of the Electrochemical
Society, Vol. 151, No. 3, pp. J21-J25, 2004.
- C. W. Low, M. L. Wasilik, H. Takeuchi, T.-J. King, and R. T. Howe,
“In-situ doped poly-SiGe LPCVD process using BCl3 for
post-CMOS integration of MEMS devices,” presented at the Symposium on SiGe: Materials, Processing,
and Devices (part of the 2004 Joint International Meeting of
The Electrochemical Society, The Electrochemical Society of Japan and
The Japan Society of Applied Physics), (Honolulu, Hawaii, USA),
October 2004.
- D. T. Lee, T. Osabe, and T.-J. King Liu, "Scaling
limitations for flexural beams used in electromechanical devices,"
IEEE Transactions on Electron
Devices, Vol. 56, No. 4, pp. 688-691, 2009.
MICRO/NANO-ELECTRO-MECHANICAL MEMORY AND
LOGIC DEVICES
- W. Y. Choi, H. Kam, D. Lee, J. Lai, and T.-J. King Liu, “Compact
nano-electro-mechanical non-volatile memory (NEMory) for 3D
integration,” Int’l Electron Devices
Meeting Technical Digest, pp. 603-606, 2007.
- F. Chen, H. Kam, D. Markovic, T.-J. King Liu, V.
Stojanovic and E. Alon, “Integrated circuit design with NEM relays,”
2008 IEEE/ACM International
Conference on Computer-Aided Design, pp. 750-757, 2008.
- W. Y. Choi, T. Osabe and T.-J. King Liu,
“Nano-electro-mechanical nonvolatile memory (NEMory) cell design and
scaling,” IEEE Transactions on
Electron Devices, Vol. 55, No. 12, pp. 3482-3488, 2008.
- W. Y. Choi and T.-J. King
Liu, "Reliability of nanoelectromechanical nonvolatile memory
(NEMory) cells," IEEE Electron Device
Letters, Vol. 30, No. 3, pp. 269-271, 2009.
- R. Nathanael, V. Pott, H. Kam, J. Jeon, and T.-J. King Liu,
"4-terminal relay technology for complementary logic," presented at
the 2009 IEEE International Electron Devices Meeting
(Baltimore, Maryland, USA), December 2009.
- H. Kam, V. Pott, R. Nathanael, J. Jeon, E. Alon, and T.-J. King
Liu, "Design and reliability of a micro-relay technology for
zero-standby-power digital logic applications," presented at the
2009 IEEE International Electron Devices Meeting (Baltimore,
Maryland, USA), December 2009.
- Jack Raper Award for Outstanding Technology-Directions:
F. Chen, M. Spencer, R. Nathanael, C. Wang, H. Fariborzi, A.
Gupta, H. Kam, V. Pott, J. Jeon, T.-J. King Liu, D. Markovic,
V. Stojanovic, and E. Alon, "Demonstration of integrated
micro-electro-mechanical (MEM) switch circuits for VLSI applications,"
2010 International Solid State Circuits Conference (San
Francisco, California, USA), pp. 150-151, 2010.
- J. Jeon, V. Pott, H. Kam, R. Nathanael, E. Alon, and T.-J. King
Liu, "Perfectly complementary relay design for digital logic
applications," IEEE Electron Device Letters, Vol. 31, No. 4,
pp. 371-373, 2010.
- J. Jeon, V. Pott, H. Kam, R. Nathanael, E. Alon, and T.-J. King
Liu, "Seesaw relay logic and memory circuits," IEEE/ASME
Journal of MicroElectroMechanical Systems, Vol. 19, No. 4, pp.
1012-1014, 2010.
- J. Jeon, R. Nathanael, V. Pott, and T.-J. King Liu,
"Four-terminal relay design for improved body effect," IEEE
ELectron Device Letters, Vol. 31, No. 5, pp. 515-517, 2010.
- R. Nathanael, V. Pott, H. Kam, J. Jeon, E. Alon, and T.-J. King
Liu, "Four-terminal-relay body-biasing schemes for complementary
logic circuits," IEEE Electron Device Letters, Vol. 31, No.
8, pp. 890-892, 2010.
- H. Fariborzi, M. Spencer, V. Karkare, J. Jeon, R. Nathanael, C.
Wang, F. Chen, H. Kam, V. Pott, T.-J. King Liu, E. Alon, V.
Stojanovic, and D. Markovic, "Analysis and demonstration of MEM-relay
power gating," presented at the 2010 Custom Integrated Circuits
Conference (San Jose, California, USA), September 2010.
- Invited: V. Pott, H. Kam, R. Nathaniel, J. Jeon,
E. Alon, and T.-J. King Liu, "Mechanical computing redux:
Relays for integrated circuit applications," Proceedings of the
IEEE, Vol. 98, No. 12, pp. 2076-2094, 2010.
- H. Kam, E. Alon, and T.-J. King Liu, "A predictive contact
reliability model for MEM logic switches," presented at the 2010
IEEE International Electron Devices Meeting (San Francisco,
California, USA), December 2010.
- Invited: T.-J. King Liu, J. Jeon, R.
Nathanael, H. Kam, V. Pott, and E. Alon, "Prospects for MEM-relay
logic switch technology," presented at the IEEE International
Electron Devices Meeting (San Francisco, California, USA),
December 2010.
- H. Kam, T.-J. King Liu, V. Stojanovic, D. Markovic, and E.
Alon, "Design, optimization and scaling of MEM relays for
ultra-low-power digital logic," IEEE Transactions on Electron
Devices, Vol. 58, No. 1, pp. 236-250, 2011.
- M. Spencer, F. Chen, C. Wang, R. Nathanael, H. Fariborzi, A.
Gupta, H. Kam, V. Pott, J. Jeon, T.-J. King Liu, D. Markovic,
E. Alon, and V. Stojanovic, "Demonstration of integrated
micro-electro-mechanical relay circuits for VLSI applications,"
IEEE Journal of Solid-State Circuits, Vol. 46, No. 1, pp.
308-320, 2011.
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