PATENTS
go back to Tsu-Jae's home page

  1. U.S. Patent 5,250,818, "Low Temperature Germanium-Silicon on Insulator Thin-Film Transistor" (with K. C. Saraswat), October 5, 1993.
  2. U. S. Patent 5,401,982, "Reducing Leakage Current in a Thin-Film Transistor with Charge Carrier Densities that Vary in Two Dimensions" (with M. G. Hack), March 28, 1995.
  3. U. S. Patent 5,707,744, "Solid Phase Epitaxial Crystallization of Amorphous Silicon Films on Insulating Substrates" (with J. H. Ho), January 13, 1998.
  4. U. S. Patent 5,893,949, "Solid Phase Epitaxial Crystallization of Amorphous Silicon Films on Insulating Substrates" (with J. H. Ho), April 13, 1999.
  5. U. S. Patent 6,210,988, "Polycrystalline silicon germanium films for forming micro-electro-mechanical systems" (with A. Franke and R. T. Howe), April 3, 2001.
  6. U.S. Patent 6,413,802, "FinFET transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture" (with C. Hu, V. Subramanian, L. Chang, X. Huang, Y.-K. Choi, J. T. Kedzierski, N. Lindert, J. Bokor, and W.-C. Lee), July 2, 2002.
  7. Taiwan Patent 154458, "Multiple-Thickness Gate Oxide Formed by Oxygen Implantation" (with Y.-C. King and C. Hu), August 16, 2002.
  8. U.S. Patent 6,448,622, "Polycrystalline silicon-germanium films for micro-electromechanical systems application" (with A. Franke and R. T. Howe), September 10, 2002.
  9. U.S. Patent 6,479,862, "Charge trapping device and method for implementing a transistor having a negative differential resistance mode" (with D. K. Y. Liu), November 12, 2002.
  10. U.S. Patent 6,512,274, "CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same" (with D. K. Y. Liu), January 28, 2003.
  11. U.S. Patent 6,518,589, "Dual mode FET & logic circuit having negative differential resistance mode," February 11, 2003.
  12. U.S. Patent 6,559,470, "Negative differential resistance field effect transistor (NDR-FET) and circuits using the same," May 6, 2003.
  13. U.S. Patent 6,567,292, "Negative differential resistance (NDR) element and memory with reduced soft error rate," May 20, 2003.
  14. U.S. Patent 6,594,193, "Charge pump for negative differential resistance transistor," July 15, 2003.
  15. U.S. Patent 6,596,617, "CMOS compatible process for making a tunable negative differential resistance (NDR) device" (with D. K. Y. Liu), July 22, 2003.
  16. U.S. Patent 6,664,601, Method of operating a dual mode FET & logic circuit having negative differential resistance mode," December 16, 2003.
  17. U.S. Patent 6,680,245, "Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process" (with D. K. Y. Liu), January 20, 2004.
  18. U.S. Patent 6,686,267, "Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode," February 3, 2004.
  19. U.S. Patent 6,686,631, "Negative differential resistance (NDR) device and method of operating same" (with D. K. Y. Liu), February 3, 2004.
  20. U.S. Patent 6,693,027, "Method for configuring a device to include a negative differential resistance (NDR) characteristic" (with D. K. Y. Liu), February 17, 2004.
  21. U.S. Patent 6,700,155, "Charge trapping device and method for implementing a transistor having a configurable threshold" (with D. K. Y. Liu), March 2, 2004.
  22. U.S. Patent 6,724,024, "Field effect transistor pull-up/load element," April 20, 2004.
  23. U.S. Patent 6,724,655, "Memory cell using negative differential resistance field effect transistors," April 20, 2004.
  24. U.S. Patent 6,727,548, "Negative differential resistance (NDR) element and memory with reduced soft error rate," April 27, 2004.
  25. U.S. Patent 6,753,229, "Multiple-thickness gate oxide formed by oxygen implantation" (with Y.-C. King and C. Hu), June 22, 2004.
  26. U.S. Patent 6,754,104, "Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET," June 22, 2004.
  27. U.S. Patent 6,794,234, "Dual work function CMOS gate technology based on metal interdiffusion" (with I. Polishchuk, P. Ranade, and C. Hu), September 21, 2004.
  28. U.S. Patent, 6,795,337, "Negative differential resistance (NDR) elements and memory device using the same," September 21, 2004.
  29. U.S. Patent 6,806,117, "Methods of testing/stressing a charge trapping device," October 19, 2004.
  30. U.S. Patent 6,812,084, "Adaptive negative differential resistance device," November 2, 2004.
  31. U.S. Patent 6,847,562, "Enhanced read and write methods for negative differential resistance (NDR) based memory device," January 25, 2005.
  32. U.S. Patent 6,849,483, "Charge trapping device and method of forming the same," February 1, 2005.
  33. U.S. Patent 6,853,035, "Negative differential resistance (NDR) memory device with reduced soft error rate," February 8, 2005.
  34. U.S. Patent 6,855,994, "Multiple-thickness gate oxide formed by oxygen implantation" (with Y.-C. King and C. Hu), February 15, 2005.
  35. U.S. Patent 6,861,707, "Negative differential resistance (NDR) memory cell with reduced soft error rate", March 1, 2005.
  36. U.S. Patent 6,864,104, "Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects," March 8, 2005.
  37. U.S. Patent 6,894,327, "Negative differential resistance pull-up element," May 17, 2005.
  38. U.S. Patent 6,912,151, "Negative differential resistance (NDR) based memory device with reduced body effects," June 28, 2005.
  39. U.S. Patent 6,933,548, "Negative differential resistance load element," August 23, 2005.
  40. U.S. Patent 6,956,262, "Charge trapping pull up element," October 15, 2005.
  41. U.S. Patent 6,969,894, "Variable threshold semiconductor device and method of operating same" (with D. K. Y. Liu), November 29, 2005.
  42. U.S. Patent 6,972,465, "CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same" (with D. K.-K. Liu), December 6, 2005.
  43. U.S. Patent 6,979,580, "Process for controlling performance characteristics of a negative differential resistance (NDR) device," December 9, 2005.
  44. U.S. Patent 6,980,467, "Method of forming a negative differential resistance device," December 27, 2005.
  45. U.S. Patent 6,990,016, "Method of making memory cell utilizing negative differential resistance devices," January 24, 2006.
  46. U.S. Patent 7,005,711, "N-channel pull-up element and logic circuit," February 28, 2006.
  47. U.S. Patent 7,012,833, "Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)," March 14, 2006.
  48. U.S. Patent 7,012,842, "Enhanced read and write methods for negative differential resistance (NDR) based memory device," March 14, 2006.
  49. U.S. Patent 7,015,536, " Charge trapping device and method of forming the same," March 21, 2006.
  50. U.S. Patent 7,016,224, "Two terminal silicon based negative differential resistance device," March 21, 2006.
  51. U.S. Patent 7,060,524, "Methods of testing/stressing a charge trapping device," June 13, 2006.
  52. U.S. Patent 7,067,873, "Charge trapping device" (with D. K. Y. Liu), June 27, 2006.
  53. U.S. Patent 7,084,407, "Ion beam extractor with counterbore" (with Q. Ji, K. Standiford, and K.-N. Leung), August 1, 2006.
  54. U.S. Patent 7,095,659, "Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device," August 22, 2006.
  55. U.S. Patent 7,098,472, "Negative differential resistance (NDR) elements and memory device using the same," August 29, 2006.
  56. U.S. Patent 7,109,078, "CMOS compatible process for making a charge trapping device" (with D. K. Y. Liu), September 19, 2006.
  57. U.S. Patent 7,113,423, "Method of forming a negative differential resistance device," September 26, 2006.
  58. U.S. Patent 7,141,858, "Dual work function CMOS gate technology based on metal interdiffusion" (with I. Polishchuk, P. Ranade, and C. Hu), November 28, 2006.
  59. U.S. Patent 7,186,619, "Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET," March 6, 2007.
  60. U.S. Patent 7,186,621, "Method of forming a negative differential resistance device," March 6, 2007.
  61. U.S. Patent 7,187,028, "Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects," March 6, 2007.
  62. U.S. Patent 7,190,050, "Integrated circuit on corrugated substrate" (with V. Moroz), March 13, 2007.
  63. U.S. Patent 7,220,636, "Process for controlling performance characteristics of a negative differential resistance (NDR) device," May 22, 2007.
  64. U.S. Patent 7,247,887, "Segmented channel MOS transistor" (with V. Moroz), July 24, 2007.
  65. U.S. Patent 7.254,050, "Method of making adaptive negative differential resistance device," August 7, 2007.
  66. U.S. Patent 7,256,107, "Damascene process for use in fabricating semiconductor structures having micro/nano gaps" (with H. Takeuchi, E. P. Quevy, and R. T. Howe), August 14, 2007.
  67. U.S. Patent 7,265,008, "Method of IC production using corrugated substrate"(with V. Moroz), September 4, 2007.
  68. U.S. Patent 7,266,010, "Compact static memory cell with non-volatile storage capability," September 4, 2007.
  69. U.S. Patent 7,453,083, "Negative differential resistance field effect transistor for implementing a pull up element in a memory cell," November 18, 2008.
  70. U.S. Patent 7,494,933, "Method for achieving uniform etch depth using ion implantation and timed etch," February 24, 2009.
  71. U.S. Patent 7,508,031, "Enhanced segmented channel MOS transistor with narrowed base regions" (with Q. Lu), March 24, 2009.
  72. U.S. Patent 7,528,465, "Integrated circuit on corrugated substrate" (with V. Moroz), May 5, 2009.
  73. U.S. Patent 7,537,866, "Patterning a single integrated circuit layer using multiple masks and multiple masking layers," May 26, 2009.
  74. U.S. Patent 7,557,009,"Process for controlling performance characteristics of a negative differential resistance (NDR) device," July 7, 2009.
  75. U.S. Patent 7,560,201, "Patterning a single integrated circuit layer using multiple masks and multiple masking layers," July 14, 2009.
  76. U.S. Patent 7,605,449, "Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material" (with Q. Lu), October 20, 2009.
  77. U.S. Patent 7,629,640, "Two bit/four bit SONOS flash memory cell" (with M. She), December 8, 2009.
  78. U.S. Patent 7,649, 230, "Complementary field-effect transistors having enhanced performance with a single capping layer" (with K. Shin), January 19, 2010.
  79. U.S. Patent 7,710,771, "Method and apparatus for capacitorless double-gate storage" (with C. Kuo), May 4, 2010.
  80. U.S. Patent 7,807,523, "Sequential selective epitaxial growth" (with Qiang Lu), October 5, 2010. 
  81. U.S. Patent 7,839,710, "Nano-electro-mechanical memory cells and devices" (with H. Kam), November 23, 2010.
  82. U.S. Patent 7,989,862, "Stress-enhanced performance of a Finfet using surface/channel orientations and strained capping layers" (with V. Moroz), May 10, 2011.
  83. U.S. Patent 7,960,232, "Methods of designing an integrated circuit on corrugated substrate" (with V. Moroz), June 14, 2011.
  84. U.S. Patent 7,995,380, "Negative differential resistance pull up element for DRAM," August 9, 2011.
  85. U.S. Patent 8,043,943, "Low-temperature formation of polycrystalline semiconductor films via enhanced metal-induced crystallization" (with R. Maboudian, F. W. DelRio and J. Lai), October 25, 2011.
  86. U.S. Patent 8,044,442, "Metal-insulator-metal (MIM) switching devices" (with H. Kam), October 25, 2011.
  87. U.S. Patent 8,329,559, "Damascene process for use in fabricating semiconductor structures having micro/nano gaps" (with H. Takeuchi, E. P. Quevy, and R. T. Howe), December 11, 2012.
  88. U.S. Patent 8,349,668, "Stress-enhanced performance of a FinFET using surface/channel orientations and strained capping layers" (with V. Moroz), January 8, 2013.
  89. U.S. Patent 8,399,183, "Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers," March 19, 2013.
  90. U.S. Patent 8,592,109, "Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers," November 26, 2013.

Back to top

Last updated December 1, 2013