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Beyond the utmost bound of human thought." - Ulysses by Alfred Tennyson

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This work is motivated by C.K. Prahald's book, "The Fortune at the Bottom of the Pyramid: Eradicating Poverty through Profits", and the work by UC Berkeley's TIER group. This paper analyzed various network architectures to identify the one that best suits the requirements of rural developing regions. We use the Akshaya Network located in Kerala, India as a case study, and show that a wireless network using WiFi for the backhaul, CDMA450 for the access network, and shared PCs for end user devices has the lowest deployment cost. However, if we include the expected spectrum licensing cost for CDMA450, a network with lease exempt spectrum using WiFi for the backhaul and WiMax for access is the most economically attractive option. Furthermore, a significant part of all costs are still regulatory with regulation representing 45.5% of the overall CapEx and 5 year OpEx. The details of this work can be found here and here.

This work was profiled by Christian Science Monitor in their article Solar power may soon bring the Web to remote areas.

We developed this switch when I was working at the Microelectronics Design Center at Infineon Technologies, Singapore. The chip was called Purple (PLF2800) – it was a configurable Gigabit Ethernet Switch with 8 Gigabit (GE) ports. Each Gigabit port could function as 8 Fast Ethernet (FE) ports yielding the following commonly used configurations – 48FE+2GE, 32FE+4GE, 24FE+5GE and 8GE. Purple featured a novel stacking mechanism, a token bucket based ingress bandwidth limiting engine, a novel packet classification engine and extensive Virtual LAN/Quality of Service (QoS) support. We conceptualized and implemented modeling strategy for Purple using Verisity Design’s e verification language for verifying architectural performance for unicast and multicast wire-speed traffic patterns. The e models were made bit accurate and used to expedite module level development. The architectural innovations of the switch can be found here and here.

7 patent applications filed on various aspects of the architecture.

In this project I investigated the design of DET flip-flops. DET flip-flops can latch in new data at every (positive and negative) clock edge. Hence they offer the potential of doubling the speed of operation with marginal increase in power. The first design I came up with attempted to reuse as many transistors as possible. Details of this design can found here. Next I developed a methodology to design double edge-triggered flip-flops using any two latches. This methodology can be found here.