Sayak Ray

Graduate Student
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley
Email: myfirstname at eecs dot berkeley dot edu
Contact Details  


Hello, and welcome to my web-space. I am an EECS graduate student, advised by Prof. Robert K. Brayton, and a member of BVSRC, DOP Center, and DMA. In our group, we address various problems on verification, and synthesis of hardware systems. My own research focusses on scalable liveness verification, as detailed below. A copy of my resume is available here (here is a shorter version).

Research Interest

In general, I am interested in tools, algorithms, and methodologies for rigorous analysis of systems. In my dissertation research, I am focussing on scalable liveness verification techniques for hardware systems. My interest spans over general, as well as system specific reasoning for liveness. In particular, I am investigating liveness problems for communication fabrics. I have dabbled a bit in synthesis, and UML-based software testing, and verification.

Open Source Development

Download ABC augmented with lieveness verification capabilities from here. For general help on ABC, please visit the ABC homepage

Publications

Disclaimer: Papers are made available on this webpage to ensure timely dissemination of research results. Copyright and all rights therein are retained by authors or other copyright holders.

Refereed Conference and Workshop Papers

  • Sayak Ray, Robert K. Brayton "Scalable progress verification in credit-based flow-control systems", DATE 2012. PDF
  • Sayak Ray, Alan Mishchenko, Niklas Een, Robert K. Brayton, Stephen Jang, Chao Chen "Mapping into LUT structures", DATE 2012. PDF
  • Sayak Ray, Robert K. Brayton "Well-foundedness in Credit-Based Flow-Control Systems", IWLS 2012 PDF
  • Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko and Robert K. Brayton "Enhancing ABC for stabilization verification of SystemVerilog/VHDL models", DIFTS 2011 PDF
  • Sayak Ray, Robert K. Brayton "Proving Stabilization Using Liveness to Safety Conversion", IWLS 2011 PDF
  • Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan "A Dynamic Assertion-Based Verification Platform for Validation of UML Designs", ATVA 2008 PDF
  • Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti "A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis", VLSI Design 2007 PDF

    Journal Paper

  • Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan: A dynamic assertion-based verification platform for validation of UML designs. ACM SIGSOFT Software Engineering Notes, 2012 PDF

    Technical Reports, Posters etc.

  • Sayak Ray, Baruch Sterin, Alan Mishchenko, and Robert K. Brayton, "Synthesis-guided partial hierarchy collapsing". IWLS 2010 PDF
  • Sayak Ray, Alan Mishchenko, Robert K. Brayton, Stephen Jang, and Thomas Daniel, "Minimum-perturbation retiming for delay optimization". IWLS 2010 PDF