ROBERT G. MEYER

Professor
Electrical Engineering and Computer Sciences

BIOGRAPHY

Robert G. Meyer was born on July 21, 1942, in Melbourne, Australia. He received the Bachelor of Electrical Engineering degree (First Class Honors) in 1963 from the University of Melbourne, Australia, and in 1965 he was awarded the degree of Master of Engineering Science (Honors) for his thesis entitled “Evaluation of noise parameters of bipolar and field-effect transistors.” In 1968 he was awarded the Ph.D. degree from the University of Melbourne for his thesis entitled “Signal and noise performance of transistor mixers.” He was awarded the J.J Thomson Premium for 1968 from the Institution of Electrical Engineers for research on noise in transistor mixers. In 2012 he was awarded the degree of Doctor of Engineering honoris causa by the Council of the University of Melbourne.

From January to September, 1968, Professor Meyer was employed as an Assistant Lecturer in Electrical Engineering at the University of Melbourne. Since September, 1968, he has been employed in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, where he is now National Semiconductor Distinguished Professor Emeritus. His current research interests are integrated-circuit design and device fabrication, with particular emphasis on nonlinear phenomena and noise performance. He is co-author of the book Analysis and Design of Analog Integrated Circuits, (Wiley, 1977, 1984, 1993, 2001, 2009), editor of the book Integrated Circuit Operational Amplifiers, (IEEE Press, 1978), and co-editor of the book Integrated Circuits for Wireless Communications, (IEEE Press, 1999). He has acted as a consultant on electronic circuit design for numerous companies in the electronics industry. He is a past President of the Solid-State Circuits Council of the IEEE. In 1973, 1976 and 1987 he was a Guest Editor of the IEEE Journal of Solid-State Circuits and from 1976 to 1982 he was an Associate Editor of the Journal. He is a former Associate Editor of the IEEE Transactions on Circuits and Systems. In 1975 he was a Visiting Professor in the Electrical Engineering Department of the Catholic University of Leuven, Belgium, and in 1996 and 2003, he was a Visiting Professor in the Electrical Engineering Department of Columbia University, New York. In 2003, he received the IEEE Leon K. Kirchmayer Graduate Teaching Award for distinguished graduate teaching and mentoring.

Professor Meyer is a Fellow of the IEEE.

PUBLICATIONS
  1. “Noise in Transistor Mixers at Low Frequencies,” Proc. IEE, Vol. 114, May 1967, pp. 611-618.

  2. “Signal Processes in Transistor Mixer Circuits at High Frequencies,” Proc. IEE, Vol. 114, November 1967, pp. 1605-1612.

  3. “Noise in Transistor Mixers at High Frequencies,” Proc. IEE, Vol. 115, April 1968, pp. 487-495.

  4. “Integrated Circuit Mixers,” IEEE NEREM Record, Vol. 12, 1970, pp. 62-63.

  5. “CANCER: Computer Analysis of Nonlinear Circuits Excluding Radiation,” (with R. Rohrer, L.W. Nagel and L. Weber), IEEE ISSCC Digest, Vol. 14, 1971, pp. 124-125.

  6. “Computationally Efficient Electronic Circuit Noise Calculations,” (with R.A. Rohrer, L.W. Nagel and L. Weber), IEEE J. Solid-State Circuits, Vol. SC-6, No. 4, August 1971, pp. 204-213.

  7. “Nonlinearity and Crossmodulation in Field-Effect Transistors,” (with D.M. Miller), IEEE J. Solid-State Circuits, Vol. SC-6, No. 4, August 1971, pp. 244-250.

  8. “Crossmodulation and Intermodulation in Amplifiers at High Frequencies,” (with M.J. Shensa and R. Eschenbach), IEEE J. Solid-State Circuits, Vol. SC-7, No. 1, February 1972, pp. 16-23.

  9. “Characterization and Measurement of the Base and Emitter Resistances of Bipolar Transistors,” (with W.M. Sansen), IEEE J. Solid-State Circuits, Vol. SC-7, No. 6, December 1972, pp. 492-498.

  10. “An Integrated Wide-Band Variable-Gain Amplifier with Maximum Dynamic Range,” (with W.M. Sansen), “Proceedings, 1973 IEEE International Symposium on Circuit Theory,” Toronto, Canada, April 1973, pp. 235-238. Published in full in IEEE J. Solid-State Circuits, Vol. SC-9, No. 4, August 1974, pp. 159-166.

  11. “Computer Simulation of 1/f Noise Performance of Electronic Circuits,” (with L. Nagel and S. Lui), IEEE J. Solid-State Circuits, Vol. SC-8, No. 3, June 1973, pp. 237-240.

  12. “Distortion in Bipolar Transistor Variable-Gain Amplifiers,” with W.M. Sansen), IEEE J. Solid-State Circuits, Vol. SC-8, No. 4, August 1973, pp. 175-182.

  13. “Recent Advances in Monolithic Operational Amplifier Design,” (with P.R. Gray), IEEE Trans. on Circuit Theory, Vol. CAS-21, No. 3, May 1974, pp. 317-327.

  14. “A Wide-Band Ultralinear Amplifier from 3 to 300 MHz,” (with R. Eschenbach and R. Chin), IEEE J. Solid-State Circuits, Vol. SC-9, No. 4, August 1974, pp. 167-175.

  15. “A Wide-Band Feedforward Amplifier,” (with R. Eschenbach and W. Edgerley), IEEE J. Solid-State Circuits, Vol. SC-9, No. 6, December 1974, pp. 422-428.

  16. “Relationship Between Frequency Response and Settling Time of Operational Amplifiers,” (with B.Y. Kamath and P.R. Gray), IEEE J. Solid-State Circuits, Vol. SC-9, No. 6, December 1974, pp. 347-352.

  17. “Distortion in Variable-Capacitance Diodes,” (with M.L. Stephens), Proceedings, Eighth Asilomar Conference on Circuits, Systems and Computers, December 1974, pp. 165-167. Published in full in IEEE J. Solid-State Circuits, Vol. SC-10, No. 1, February 1975, pp. 47-54.

  18. “Modular Single-Stage Universal Logic Gate,” (with J.R. Gaskill, J.H. Flint, L.R. Weill, and L.J. Micheel), IEEE ISSCC Digest, Vol. 18, 1975, pp. 14-15. Published in full in IEEE J. Solid-State Circuits, Vol. SC-11, No. 4, August 1976, pp. 529-538.

  19. “The Differential Pair as a Triangle-Sine Wave Converter,” (with W.M.C. Sansen, S. Lui and S. Peeters), IEEE J. Solid-State Circuits, Vol. SC-11, June 1976, pp. 418-420.

  20. “LSI Multiplier Using High Speed ULG,” (with J.R. Gaskill, J.H. Flint, L.R. Weill, and L.J. Micheel), IEEE J. Solid-State Circuits, Vol. SC-11, No. 4, August 1976, pp. 539-544.

  21. “Transistor Design for Low Distortion at High Frequencies,” (with H. Abraham), IEEE Trans. Electron Devices, Vol. ED-23, No. 12, December 1976, pp. 1290-1297.

  22. “A Low-Distortion Monolithic Wideband Amplifier,” (with K.H. Chan), IEEE ISSCC Digest, Vol. 20, 1977, pp. 208-209. Published in full in IEEE J. Solid-State Circuits, Vol. SC-12, No. 6, December 1977, pp. 685-690.

  23. “An Extended Integral Charge Control Transistor Model for High Current DC, AC and Distortion Analysis,” (with D.G. Duff), IEEE ISCAS Proceedings, 1977, pp. 19-22.

  24. Analysis and Design of Analog Integrated Circuits, Wiley, New York, 1977 (with P.R. Gray).

  25. “A High-Voltage Analog-Compatible I2L Process,” (with D.J. Allstot, T. Wei, S. Lui, and P.R. Gray), IEEE IEDM Digest, December 1977, pp. 175-177. Published in full in IEEE J. of Solid-State Circuits, Vol. SC-13, No. 4, August 1978, pp. 479-483.

  26. “A New NMOS Temperature-Stable Voltage Reference,” (with R. Blauschild, P. Tucci, and R. Muller), IEEE ISSCC Digest, Vol. 21, 1978, pp. 50-51. Published in full in IEEE J. Solid-State Circuits, Vol. SC-13, No. 6, December 1978, pp. 767-774.

  27. Integrated-Circuit Operational Amplifiers, (IEEE Press, 1978) Editor.

  28. “An Ion-Implanted Sub-Surface Monolithic Zener Diode,” (with S. Lui and N. Kwan), IEEE J. Solid-State Circuits, Vol. SC-14, No. 4, August 1979, pp. 782-784.

  29. “MOS Crystal Oscillator Design,” (with D. Soo), IEEE J. Solid-State Circuits, Vol. SC-15, No. 2, April 1980, pp. 222-228.

  30. “High Frequency Bipolar-JFET-I2L Process,” (with S.K. Lui), IEEE IEDM Digest, 1980, pp. 382-385. Published in full in IEEE Trans. on Electron Devices, Vol. ED-29, No. 8, August 1982, pp. 1319-1323.

  31. “A Four-Terminal Wideband Monolithic Amplifier,” (with R. Blauschild), IEEE ISSCC Digest, Vol. 24, 1981, pp. 186-187. Published in full in IEEE J. Solid-State Circuits, Vol. SC-16, No. 6, December 1981, pp. 634-638.

  32. “A High-Frequency Temperature-Stable Monolithic VCO,” (with J. Kukielka), IEEE ISSCC Digest, Vol. 24, pp. 126-127. Published in full in IEEE J. Solid-State Circuits, Vol. SC-16, No. 6, December 1981, pp. 639-647.

  33. “Conditions for Start-Up in Crystal Oscillators,” (with M. Unkrich), IEEE J. Solid-State Circuits, Vol. SC-17, No. 1, February 1982, pp. 87-90.

  34. “A 4-Quadrant MOS Analog Multiplier,” (with D. Soo), IEEE ISSCC Digest, Vol. 25, February 1982, pp. 36-37. Published in full in IEEE J. Solid-State Circuits, Vol. SC-17, No. 6, December 1982, pp. 1174-1179.

  35. “MOS Operational Amplifier Design - A Tutorial Overview,” (with P.R. Gray), IEEE J. Solid-State Circuits, Vol. SC-17, No. 6, December 1982 pp. 969-983.

  36. “Noise in Relaxation Oscillators,” (with A. Abidi), IEEE J. Solid-State Circuits, Vol. SC-18, No. 6, December 1983, pp. 794-804.

  37. Analysis and Design of Analog Integrated Circuits, Second Edition, Wiley, New York, 1984, (with P.R. Gray).

  38. “A One-Pin Crystal Oscillator for VLSI Circuits,” (with J. Santos), IEEE J. Solid-State Circuits, Vol. SC-19, No. 2, April 1984, pp. 228-236.

  39. “A 750 MS/S NMOS Latched Comparator,” (with D. Soo, et. al.), IEEE ISSCC Digest, Vol. 28, 1985, pp. 146-147.

  40. “Triangle-to-Sine Wave Conversion with MOS Technology,” (with J. Fattaruso), IEEE J. Solid-State Circuits, Vol. SC-20, No. 2, April 1985, pp. 623-631.

  41. “A Low Power, 5V, 150 MHz PLL with Improved Linearity,” (with R.A. Blauschild), IEEE ICCE Digest, June 1985, pp. 122-123.

  42. “Low Distortion Switched-Capacitor Filter Design Techniques,” (with K. Lee), IEEE J. Solid-State Circuits, Vol. SC-20, No. 6, December 1985, pp. 1103-1113.

  43. “A Wideband Low-Noise Monolithic Transimpedance Amplifier,” (with R.A. Blauschild), IEEE J. Solid-State Circuits, Vol. SC-21, No. 4, August 1986, pp. 530-533.

  44. “Intermodulation in High-Frequency Bipolar Transistor Integrated-Circuit Mixers,” IEEE J. Solid-State Circuits, Vol. SC-21, No. 4, August 1986, pp. 534-537.

  45. “One-Pin Crystal Oscillator,” (with J. Santos), U.S. Patent 4,600,898, July 15, 1986.

  46. “Charge-Control Analysis of the Collector-Base Space-Charge-Region Contribution to Bipolar Transistor Time Constant” (with R.S. Muller), IEEE Trans. on Electron Devices, Vol. ED-34, No. 2, February 1987, pp. 450-452.

  47. “A Matched Impedance NMOS Amplifier,” (with K.Y. Toh, IEEE ISSCC Digest, Vol. 30, 1987, pp. 168-169.

  48. “Nonlinear Analog Function Synthesis with MOS Technology,” (with J. Fattaruso), IEEE 1987 Custom Integrated Circuits Conference Digest, pp. 647-650.

  49. “Wideband, Low-Noise, Matched Impedance Amplifiers in Submicron MOS Technology,” (with K.Y. Toh, IEEE J. Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pp. 1031-1040.

  50. “MOS Analog Function Synthesis,” (with J. Fattaruso), IEEE J. Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pp. 1056-1063.

  51. “A 250 MHz Monolithic Voltage-Controlled Oscillator,” (with T.P. Liu), IEEE ISSCC Digest,Vol. 31, February 1988, pp. 22-23. Published in full in IEEE J. Solid-State Circuits, Vol. 25, No. 2, April 1990, pp. 555-561.

  52. “A 350 MHz Bipolar Monolithic PLL,” (with M. Soyeur), IEEE CICC Digest, May 1988, pp. 961-964.

  53. “An Engineering Model for Short-Channel MOS Devices,” (with K.Y. Toh and P. Ko), IEEE J. Solid-State Circuits, Vol. SC-23, No. 4, August 1988, pp. 950-958.

  54. “A Wideband Class AB Monolithic Power Amplifier,” (with W.D. Mack), IEEE J. Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 7-12.

  55. “A Wideband Class-B Video Output Driver,” (with R.A. Blauschild, et al.), IEEE ISSCC Digest, Vol. 32, February 1989, pp. 70-71. Published in full in IEEE J. Solid-State Circuits, Vol. 24, No. 6, December 1989, pp. 1529-1538.

  56. “High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology,” (with M. Soyuer), IEEE J. Solid-State Circuits, Vol. 24, No. 3, June 1989, pp. 787-795.

  57. “A New Wideband Darlington Amplifier,” (with C.T. Armijo), IEEE J. Solid-State Circuits, Vol. 24, No. 4, August 1989, pp. 1105-1109.

  58. “Frequency Limitations of a Conventional Phase-Frequency Detector,” (with M. Soyeur), IEEE J. Solid-State Circuits, Vol. 25, No. 4, August 1990, pp. 1019-1022.

  59. “Si IC-Compatible Inductors and LC Passive Filters,” (with N. Nguyen), IEEE J. Solid-State Circuits, Vol. 25, No. 4, August 1990, pp. 1028-1031.

  60. “Wideband Class AB CRT Cathode Drives,” U.S. Patent 4,999,586, March 12, 1991.

  61. “A DC to 1-GHz Differential Monolithic Variable-Gain Amplifier,” (with W.D. Mack), IEEE J. Solid-State Circuits, Vol. 26, No. 11, November 1991, pp. 1673-1680.

  62. “Active Bypass for Inhibiting High-Frequency Supply Voltage Variations in Integrated Circuits,” U.S. Patent 5,049,764, September 17, 1991.

  63. “A Si Bipolar Monolithic RF Bandpass Amplifier,” (with N. Nguyen), IEEE J. Solid-State Circuits, Vol. 27, No. 1, January 1992, pp. 123-127.

  64. “A 1.8 GHz Monolithic LC Voltage-Controlled Oscillator,” (with N. Nguyen), IEEE ISSCC Digest, Vol. 35, February 1992, pp. 158-159. Published in full in IEEE J. Solid-State Circuits, Vol. 27, No. 3, March 1992, pp. 444-450.

  65. “Principles of Wideband Monolithic Feedback Amplifier Design,” (with C.D. Hull), International Journal of High Speed Electronics, Vol. 3, No. 1, March 1992, pp. 53-93.

  66. “Start-up and Frequency Stability in High-Frequency Oscillators,” (with N. Nguyen), IEEE J. Solid-State Circuits, Vol. 27, No. 5, May 1992, pp. 810-820.

  67. Analysis and Design of Analog Integrated Circuits, Third Edition, Wiley, New York, 1992, (with P.R. Gray).

  68. “New ESD Protection Schemes for BiCMOS Processes with Application to Cellular Radio Design,” (with W.D. Mack), IEEE ISCAS Proceedings, May 1992, pp. 2699-2702.

  69. “A Systematic Approach to the Analysis of Noise in Mixers,” (with C.D. Hull), IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 40, No. 12, December 1993, pp. 909-919.

  70. “A 1-GHz BiCMOS RF Front-End IC,” (with W.D. Mack), IEEE J. Solid-State Circuits, Vol. 29, No. 3, March 1994, pp. 350-355.

  71. “A Wideband Low-Noise Variable-Gain BiCMOS Transimpedance Amplifier,” (with W.D. Mack), IEEE J. Solid-State Circuits,Vol. 29, No. 6, June 1994, pp. 701-706.

  72. “Design Techniques for 1GHz Downconversion ICs Fabricated in a 1µm 13GHz BiCMOS Process,” (with W.D. Mack), Analog Circuit Design, Kluwer, Boston, 1994, pp. 247-262.

  73. “Low-Power Monolithic RF Peak Detector Analysis,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 1, January 1995, pp. 65-67.

  74. “Future Directions in Silicon ICs for RF Personal Communications,” (with P.R. Gray), IEEE Custom Integrated Circuits Conference Digest, May 1995, pp. 83-90.

  75. “Modeling and Analysis of Substrate Coupling in Integrated Circuits,” (with R. Gharpurey), IEEE Custom Integrated Circuits Conference Digest, May 1995, pp. 125-128.  Published in full in IEEE J. Solid-State Circuits, Vol. 31, No. 3, March 1996, pp. 344-353.

  76. “Blocking and Desensitization in RF Amplifiers,” (with A. Wong), IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, August 1995, pp. 944-946.

  77. “Analysis and Simulation of Substrate Coupling in Integrated Circuits,” (with R. Gharpurey), International Journal of Circuit Theory and Applications, Vol. 23, No. 4, July-August 1995, pp. 381-394.

  78. “Monolithic AGC Loop for a 160 Mb/s Transimpedance Amplifier,” (with W.D. Mack), IEEE Journal of Solid-State Circuits, Vol. 31, No. 9, September 1996, pp. 1331-1335.

  79. “A 2.5 GHz BiCMOS Transceiver for Wireless LAN,” (with W.D. Mack and J. Hageraats), IEEE 1997 ISSCC Digest, pp. 310-311. Published in full in IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, December 1997, pp. 2097-2104.

  80. “Analysis and Optimization of Monolithic Inductors and Transformers for RF ICs,” (with A.M. Niknejad), IEEE 1997 CICC Digest, pp. 375-378.

  81. “A 2.4 GHz Monolithic Mixer for Wireless LAN Applications,” (with K.L. Fong), IEEE 1997 CICC Digest, pp. 185-188.

  82. “A Class AB Monolithic Mixer for 900 MHz Applications,” (with K.L. Fong and C.D. Hull), IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, August 1997, pp. 1166-1172.

  83. “High-Frequency Nonlinearity Analysis of Common-Emitter and Differential-Pair Trans­conductance Stages,” (with K.L. Fong), IEEE Journal of Solid-State Circuits, Vol. 33, No. 4, April 1998, pp. 548-555.

  84. “Numerically Stable Green Function for Modeling and Analysis of Substrate Coupling in Integrated Circuits,” (with A. Niknejad and R. Gharpurey), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 4, April 1998, pp. 305-315.

  85. “Analysis, Design and Optimization of Spiral Inductors and Transformers for RF ICs,” (with A.M. Niknejad), IEEE Journal of Solid-State Circuits, Vol. 33, No. 10, October 1998, pp. 1470-1481.

  86. Integrated Circuits for Wireless Communications, IEEE Press, 1999, A. Abidi, P. Gray and R.G. Meyer, Editors.

  87. “Substrate Optimization Based on Semi-Analytical Techniques,” (with E. Chabon, R. Gharpurey and A. Sangiovanni-Vincentelli), IEEE Transactions on Computer-Aided Design, Vol. 18, No. 2, Feb. 1999, pp. 172-190.

  88. “Monolithic RF Active Mixer Design,” (with K.L. Fong), IEEE Transactions on Circuits and Systems,Vol. 46, No. 3, March 1999, pp. 231-239.

  89. “Noise in Current-Commutating CMOS Mixers,” (with M.T. Terrovitis), IEEE Journal of Solid-State Circuits,Vol. 34, No. 6, June 1999, pp. 772-783.

  90. “A Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications,” (with M.A. Margarit, J.L. Tham and M.J. Dean), IEEE Journal of Solid-State Circuits,Vol. 34, No. 6, June 1999, pp. 761-771.

  91. “Fully Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz,” (with M. Niknejad and J. L. Tham), Proceedings of the European Solid-State Circuits Conference, September 1999, pp. 198-201.

  92. “Wide-Dynamic-Range Variable-Gain Amplifier,” U.S. Patent 6,049,251, April 2000.

  93. “Phase Noise in LC Oscillators,” (with K. A. Kouznetsov), IEEE Journal of Solid-State Circuits,Vol.35, No. 8, August 2000, pp. 1244-1248.

  94. “Intermodulation Distortion in Current-Commutating CMOS Mixers,” (with M. T. Terrovitis), IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, October 2000, pp. 1461-1473.

  95. Design, Simulation and Applications of Inductors and Transformers for Si RF ICs, (with A. M. Niknejad), Kluwer, 2000.

  96. “Analysis of Eddy Current Losses over Conductive Substrates with Applications to Monolithic Inductors and Transformers,” (with A. M. Niknejad), IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 1, January 2001, pp. 166-176.

  97. Analysis and Design of Analog Integrated Circuits,Fourth Edition, (with P. R. Gray, P. J. Hurst and S. H. Lewis), Wiley, New York, 2001.

  98. Substrate Noise: Analysis and Optimization for Design, (with E. Charbon, R. Gharpurey, P. Miliozzi and A. Sangiovanni-Vincentelli), Kluwer, 2001.

  99. Trade-offs in Analog Circuit Design, (with C. Toumazou, et. al.), Kluwer, 2002.

  100. "Enhanced LC Filter with Tunable Q,” U.S. Patent 6,307,442, October 23, 2001.

  101. “Cyclostationary Noise in Radio-Frequency Communication Systems,” (with M.T. Terrovitis and K.S. Kundert), IEEE Transactions on Circuits and Systems-I. Fundamental Theory and Applications, Vol. 49, No. 11, November 2002, pp. 1666-1671.

  102. “A Wideband Low-Phase-Noise CMOS VCO,” (with A. D. Berny and A. M. Niknejad), IEEE 2003 Custom Integrated Circuits Conference Digest, pp. 555-558.

  103. “A 1.8 GHz LC VCO with 1.3 GHz Tuning Range and Mixed-Signal Amplitude Calibration,” (with A.D. Berny and A.M. Niknejad), IEEE 2004 Symposium on VLSI Circuits Digest, pp. 54-57.

  104. “A DC-10 GHz Linear-in-dB Attenuator in 0.13 µm CMOS Technology,” (with H. Dogan and A.M. Niknejad), IEEE 2004 Custom Integrated Circuits Conference Digest, pp. 609-612.

  105. “Analysis and Simulation of Spectral Regrowth in Radio Frequency Power Amplifiers,” (with B. Baytekin), IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, February 2005, pp. 370-381.

  106. “A 1.8 GHz LC VCO with 1.3 GHz Tuning Range and Digital Amplitude Calibration,” (with A.D. Berny and A.M. Niknejad), IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 909-917.

  107. “A DC-2.5 GHz Wide-Dynamic-Range Attenuator in 0.13 µm CMOS Technology,” (with H. Dogan and A.M. Niknejad), IEEE 2005 VLSI Circuits Symposium, pp. 90-93.

  108. “A 2.2 GHz Sub-Harmonic Mixer for Direct Conversion Receivers in 0.13 µm CMOS,” (with H. Jen and S. Rose), IEEE 2006 ISSCC Digest of Technical Papers, pp. 460-462.

  109. “Intermodulation Distortion in CMOS Attenuators and Switches,” (with H. Dogan), IEEE Journal of Solid State Circuits, vol. 42, No. 3, March 2007, pp. 529-539.

  110. “Analysis and Design of RF CMOS Attenuators,” (with H. Dogan and A.M. Niknejad), IEEE Journal of Solid State Circuits, vol. 43, No. 10, October 2008, pp. 2269-2283.

  111. “ESD Protection Method for Low-Breakdown Integrated Circuits,” U.S. Patent 7,518,846, April 4, 2009.

  112. “RMS Detector with Automatic Gain Control,” U.S. Patent 7,994,840, August 9, 2011.

  113. “Low Distortion MOS Attenuator,” U.S. Patent 8,390,359, March 5, 2013.

Last updated on June 21, 2013