I am a graduate student in the EECS Department at the University of California at Berkeley.
I work with Professor Krste Asanovic in the Parallel Computing Laboratory. My main research interests are
in parallel systems software and operating systems design for manycore chip multiprocessors. Previously,
I was a PhD student in the SCALE group at the MIT Computer Science and Artificial Intelligence Laboratory.

Education

University of California, Berkeley

• Ph.D. Candidate in Computer Science, August 2007 - present
  Minor in Management of Technology at the Haas School of Business

Massachusetts Institute of Technology

• Ph.D. Candidate in Computer Science, Sept. 2005 - August 2007
  Minor in Technology, Innovation, and Entrepreneurship at the
      Sloan School of Management

• M.Eng. in Electrical Engineering and Computer Science, Sept. 2005
  Winner of the 2006 Dimitris N. Chorafas Foundation Award

• S.B. in Electrical Engineering and Computer Science, June 2004

Research

Parallel Computing on Manycore Platforms

Re-architecting Operating Systems for Manycore Client Platforms
The main problem facing the multicore era is how can software utilize these cores? Existing operating
systems can be manually parallelized. However, as larger core counts are doubled each generation, the
rate at which an operating system can be parallelized will soon fall behind the rate at which hardware
parallelism will be available. Even if we find a way to scale existing operating systems to larger
core counts, another question still remains; Is the current dominant operating design, the monolithic
operating system, right for future client applications that will run on these multicore machines? To write
efficient parallel applications in the future, programmers need to deal with resource management, and
implement the resource management policies (scheduling, memory management) best for the application.
Currently parallel programmers often have to work around undesirable OS policies in order to achieve
the desired performance. This is a strong indication that existing monolithic operating system designs
are not suitable for parallel applications in the future.

We are exploring how to architect operating systems to better address the needs of parallel applications
and programmers as well as achieve better scaling to support new generations of parallel hardware. This
work is part of the Parallel Computing Laboratory at Berkeley.

Bthreads: Bare Threads Model
Previously, I worked on Bthreads, a simple, lightweight, low-level parallel programming model that allows
programmers to have efficient control over the hardware. The goal for Bthreads is to simplify the porting
of parallel applications to new multiprocessor hardware platforms. Bthreads offers thread management and
synchronization functions similar to the Posix thread model (Pthreads), as well as basic communication
primitives to send data between threads.

InfiniT Stored-Processor Machine
I also worked on the InfiniT Stored-Processor project.

AXCIS: Accelerating Simulation for Computer Architecture Design Space Exploration

AXCIS is a framework for fast and accurate microarchitectural design space exploration. AXCIS achieves
fast simulation times by exploiting repetitions in program behavior to compress a program's dynamic trace
into a form that can be used to model many machines. Given a compressed trace and a microarchitecture
configuration, the AXCIS performance model accurately estimates machine performance within seconds.

• "Accelerating Architectural Exploration using Canonical Instruction Segments"
  Rose F. Liu and Krste Asanovic
  IEEE International Symposium on Performance Analysis of Systems and Software, 2006.
  [ PDF | PDF slides | PDF slide+notes ]
  
  Short Talk at the CRA-W Grad Cohort Poster Session in April 2006, and the Boston Architecture
  Workshop in Feb. 2006. [ PDF slides ]

• "AXCIS: Rapid Processor Architectural Exploration using Canonical Instruction Segments"
  M.Eng. Thesis, Massachusetts Institute of Technology, September 2005. [ PDF ]

Thermal Characterization of Workloads

Developed an abstract analytical model to estimate processor power based on microarchitectural unit utilizations.

• "Early Stage Thermal Characterization of Workloads"
  R. F. Liu, M. Ibrahim, P. Bose, A. Buyuktosunoglu, and Z. Hu
  Presented at the CMOS Design Forum and IBM Research Summer Student Poster Session,
  IBM. T.J. Watson Research Center, NY, Aug. 2004.

• "Thermal Characterization and Floor plan–Level Visualization of Key Workloads"
  Rose F. Liu and Pradip Bose
  Presented at the CMOS Design Forum and IBM Research Summer Student Poster Session,
  IBM. T.J. Watson Research Center, NY, Aug. 2003.

Electromigration Lifetime Study of Cu Line/Via on W

• "Effects of failure criteria on the lifetime distribution of dual-damascene Cu line/via on W"
  R. F. Liu, C.-K. Hu, L. Gignac, J. M. E. Harper, J. Lloyd, X.-H. Liu, and A. K. Stamper
  Journal of Applied Physics, vol 95, p 3737, 2004. [ PDF ]
  
  Presented at the IBM Research Summer Student Poster Session,
  IBM T.J. Watson Research Center, NY, Aug. 2002.
  

Teaching

I was a graduate student instructor (GSI) for CS252 Graduate Computer Architecture, Fall 2007.

Class Projects

• "Hardware Implementation of an 802.11a Transmitter"
  Complex Digital Systems (MIT 6.884), Spring 2005.
  [ PDF | PPT slides ]

• "Learning on Bayesian Networks"
  Techniques in Artificial Intelligence (MIT 6.825), Fall 2004.
  [ PDF ]

• "Analysis of Three Bayesian Network Inference Algorithms: Variable Elimination,
  Likelihood Weighting, and Gibbs Sampling"
  Techniques in Artificial Intelligence (MIT 6.825), Fall 2004.
  [ PDF ]

• "Zebra: Peer to Peer Multicast for Live Streaming Video"
  Distributed Computer Systems Engineering (MIT 6.824), Spring 2004.
  [ PDF ]

• "Exokernel Style Operating System"
  Operating System Engineering (MIT 6.828), Fall 2003. 

• "Digital Beat Detector for a Dancing Robot"
  Introductory Digital Systems Laboratory (MIT 6.111), Spring 2002.