Charge Recycling Circuit for Leakage Power Reduction

Hanh-Phuc Le (phucle @ eecs) and Jiashu Chen (jiashu @ eecs)

In recent development of low power digital circuits, when the technology still tries to keep its speed going down deep into sub-micro scale, the in-active leakage loss becomes significant of about 30% of the total power consumption, thus, can not be ignored any more. To address the problem, sleep transistor technique, as exemplarily shown in Fig.1, which utilizes a high threshold transistor in series with digital circuits to power supply is introduced. The sleep transistor is turned on when the circuit is in computational mode and is turned off in standby mode to reduce leakage power consumption remarkably.

However, the virtual ground of the logic gates, or the drain node of the sleep transistor, which is associated with a relatively big parasitic capacitor, will drift up to near Vdd during standby mode due to the leakage current and that amount of charge drawn from supply in this mode will, then, be dumped to the ground when the circuit enters computational mode. This is apparently a loss that potentially results in increasing power consumption of the circuit, especially when the mode change comes with high frequency.

In this project, we propose a charge recycling circuit that can store the charge right before the computational mode and dump it back to the virtual ground when the circuit enters standby mode so that the virtual ground no longer has to draw a large amount of “leakage” charge from supply. The amount of energy that can be saved by this technique depends on several important parameters including how fast the circuit switches between the two modes, how large the virtual ground parasitic capacitance is and how efficient the charge recycling circuit can be built.

With that, our project is divided into two phases. First, a study will be conducted to determine the proper situation where this technique is beneficial, that most probably comes with different trade-off curves including the one shown in Fig. 2. Second, an efficient charge recycling circuit will be designed to prove this idea.

Fig. 1. Leakage reduction sleep transistor

Fig. 2. Power savings trade-off

Reference:

[1] Wei, L.; Chen, Z.; Roy, K.; Johnson, M.C.; Ye, Y.; De, V.K,“Design and optimization of dual-threshold circuits for low-voltage low-power applications” in IEEE Transactions on Volume 7, Issue 1, March 1999, pp.16 – 24.

[2] T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu and T. Sakurai, “A 0.9-V, 150-MHz, 10-mW, 4mm , 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme,” IEEE J. Solid-State Circuits, vol. 31, pp. 1770–1779, Nov. 1996.

[3] K. S. Min and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," ISSCC, pp.400-401, Feb.2003.

[4] K. S. Min and T. Sakurai, "Zigzag super cut–off CMOS (ZSCCMOS) scheme with self–saturated virtual power lines for subthreshold–leakage–suppressed sub–1–V–VDDLSI's", Proceedings of the 28th European SSCC, pp.679-682, Sept.2002.

[5] E. Pakbaznia, F. Fallah and M. Pedram “Charge recycling in MTCMOS circuits: concept and analysis,” in Proc. Design Automation Conference, pp. 97-102, 2006.

[6] James Tschanz, et. al., ‘Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors’, ISSCC Dig. Tech. Papers, pp 102 - 481, Feb. 2003.

[7] James Tschanz, et. al., ‘Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors’, JSSC, pp 1838 - 1845, Feb. 2003.