Current Research Projects:

In-situ doped n– and p–Si and Si_1-xGe_x CVD and SPE process characterization/development

Summary:  This work is key to enabling my low resistivity contact study (below).  The goal here is to develop Si and Si_1-xGe_x CVD recipes in one of our CVD furnaces that will allow us to accurately modulate Ge concentration, dopant concentration, and film thickness for thin film depositions.  This study is complemented with an SPE study to take these deposited films and crystallize them after a Si implant to break up any interfacial layer between the deposited film and the [seed] substrate.  The required Si implant energy and dose, which vary with film thickness and %Ge, are designed using TRIM with full damage cascades and some simple assumptions.

Low resistivity contacts to Si_1-xGe_x for metallic source/drain (MSD) technology

Summary:  This work focuses on developing aggressively-scaled contacts with low (~10^-8-9 Ohm-cm²) contact resistivity.  Si_1xGe_x will be used as the vehicle for this, as it enhances transmission at metal-semiconductor (M-S) junctions due to reduced bandgap and effective mass in comparison to Si.  A new contact structure design for more accurately determining contact resistivity is under fabrication, and the effects of M-S interface engineering to reducing contact resistivity will be explored here.  Optimal design points will be utilized in subsequent MOSFET fabrication.

Device modeling of Metallic Source/Drain (MSD) structures with doped extension/segregation regions

Summary:  Although this work will investigate drive current optimization in MSD MOSFETs, the main focus here is on minimizing leakage in structures that use doped extensions as a means of Schottky barrier lowering (SBL).  Although these extensions have proven effective at SBL for CoSi₂ and NiSi, the properties of these extensions (size, dopant concentration, etc.) play a role in determining the leakage floor.  Modulating the extension size results in leakage that is initially dominated by conventional P-N thermal leakage (large extension size), and then tunneling through the extension (intra-band tunneling), and then Schottky barrier tunneling (also intra-band, but different barrier shape).  ITRS leakage constraints per technology node will be used as a guide to define design windows for doped extension properties.  I hope to quantify these leakage levels and how they vary with metal workfunction, bandgap, extension doping, etc., and what the implications are for MSD MOSFET design and process flow for ultra-thin body (UTB) device structures.

3-D device modeling of advanced source/drain architectures and contact techniques

Summary:  This work focuses on determining the most appropriate source/drain and contact solutions for MOSFET designs at the decananometer (and smaller) scale.  Although MSD MOSFETs have been studied (by myself and others) for some time as a potential solution, the promise of lower series resistance within the source/drain region may be compromised by reduced contact area for UTB devices.  There may also exist a shrinking design space for such structures as the gate length is scaled, and so I am now exploring approaches that can improve this design space, and the options therein, to result in performance improvements for both HP and LSTP designs. 

Effects of quantum confinement, random dopant fluctuation, and silicide gating on specific contact resistivity to ultra-thin body MOSFETs

Summary:   As gate lengths are scaled into the deca-nanometer and eventually the nanometer regime, thin body structures such as FinFETs or ultra-thin body SOI (UTB SOI) will be required to control short channel effects.  This gives rise to challenges in source/drain series resistance, as well as contact resistance, for doped source/drain and metallic source/drain MOSFETs in this regime.  If the source/drain region is small enough, random dopant fluctuations and quantum confinement will become significant even if high dopant concentrations are used.  This study focuses on quantifying these effects and their implications for MOSFET scaling.

Effect of direct source-to-drain tunneling on source/drain, contact, and gate stack design for sub-10 nm MOSFETs

Summary:   For MOSFETs in the sub-10 nm gate length regime, direct source-to-drain tunneling (DSDT) begins to limit the off-state performance and switching integrity.  What this study focuses on is understanding how, if at all, DSDT influences MOSFET design for the gate stack, source/drain, and contact structures.  What we are also interested in is finding out what geometric and/or electrostatic tricks may be employed to minimize DSDT, in an effort to improve MOSFET scalability in the sub-10 nm regime.

Extracurricular Projects:

K-12 outreach program development:

Summary:  Outreach has always been an important part of my academic life as an engineer, for scientists and engineers who are passionate about their work can serve as an important guide and/or role model for younger students.  My previous experiences with outreach have been unfulfilling, due mostly to the superficial or “cookie cutter” nature of such programs/events.  My goal is to develop a K-12 outreach initiative that is not based on quantity so much as it is on quality, in an effort to give younger students a better appreciation of the richness of science and engineering.  The approach will place an emphasis on discussing advanced topics in an easy-to-understand manner, which may include [but are not limited to] system design (iPods, cell phones, etc.), microelectronic technology, and astronomy.

Here is a link to some notes and thoughts on the matter.  Feel free to use them at your disposal.