Nadathur R Satish

Sixth Year Graduate Student
Dept. of EECS, UC Berkeley
[nrsatish [at] eecs [dot] berkeley [dot] edu]
[http://www.eecs.berkeley.edu/~nrsatish]

Office
545W Cory Hall
Dept. of EECS
University of California, Berkeley
Berkeley, CA 94720

Home
1929 Delaware Street
Apartment 2B
Berkeley, CA 94709-2193

Purpose

Looking for a challenging research position at a top company/research lab.

 

Research Interests

Task allocation and scheduling on multi-processors, data-parallel computing, system architecture, optimization, GPU computing. I currently work on mapping parallel applications to multiprocessor architectures to optimize for throughput and/or latency, and on mapping data-parallel applications to current and future many-core architectures.

Education

2003-Present              University of California, Berkeley                           Berkeley, CA

Ph.D. in Electrical Engineering (expected Dec 2008)                                    GPA: 3.97 / 4.0
 

1999-2003                   Indian Institute of Technology, Kharagpur                         India

Bachelor of Technology (Honors) in Computer Science and Engg.           GPA: 9.67 / 10.00

Work Experience

7/2003 - Present         University of California, Berkeley                           Berkeley, CA

Graduate Student Researcher

·         Automating the mapping of high-performance parallel applications onto multiprocessor systems

·         Using stochastic optimization to perform static mapping in the presence of task variability

 

Summer of 2008        Intel Corporation                                                      Santa Clara, CA

Graduate Research Intern

·         Researched the integration of data structures in Artificial Intelligence with game physics and raytracing

·         Worked on parallelizing crowd simulations and visibility computations for many-core CPUs

 

Summer of 2007        NVIDIA Incorporated                                              Santa Clara, CA

Graduate Research Intern

·         Optimized different algorithms in the CUDA programming model for NVIDIA GPUs

 

Summer of 2005        Stretch Incorporated                                                Mountain View, CA

Summer Research Intern

·         Explored a flow from Matlab descriptions to the Stretch processor


Summer of 2001        National Semiconductor Corporation                     Munich, Germany

Summer Intern

·         Developed a SystemC simulator for a new chip

Selected Awards and Honors

2003                            Electrical Engineering Graduate Fellowship, UC Berkeley 2003
2003                            President of India Gold medal for graduating at the top of the 2003

batch at IIT Kharagpur

2002                            Charubala Devi Memorial Award for topping the junior batch
1999                            Named in the inaugural Aditya Birla Scholarship list in 1999 –

                                    awarded each year to 10 IIT students in India.
1998                            Selected to the Indian National Mathematical Olympiad

Advanced Coursework at the University of California at Berkeley

Graduate Computer Architecture                   CS252

Field-Programmable Gate Arrays                   CS294-3

Logic Synthesis                                               EE219B

Combinational Optimization                           IEOR264
Embedded Software Design                          EE249

Programming Language Design                      CS263

Publications

  1. Scheduling Task Dependence Graphs with Variable Task Execution Times onto Heterogeneous Multiprocessors, Nadathur Satish, Kaushik Ravindran and Kurt Keutzer, To Appear in the Proceedings of the 2008 International Conference on Embedded Software (EMSOFT 08), October 2008.
  2. Data-Parallel Large Vocabulary Continuous Speech Recognition on Graphics Processors, Jike Chong, Youngmin Yi, Arlo Faria, Nadathur Satish, Kurt Keutzer, Proceedings of the 1st Annual Workshop on Emerging Applications and Many Core Architecture (EAMA), pp 23-35, June 2008.
  3. A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors, Nadathur Satish, Kaushik Ravindran and Kurt Keutzer, Proceedings of the 10th International Conference on Design Automation and Test in Europe (DATE 07), pp 57-62, April, 2007
  4. Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling, Jike Chong, Nadathur Rajagopalan Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer, Proceedings of 2007 International Conference on Multimedia and Expo, pp 1874-1877, July 2007
  5. An Automated Exploration Framework for FPGA-Based Soft Multiprocessor Systems, Yujia Jin, Nadathur Satish, Kaushik Ravindran and Kurt Keutzer, Proceedings of the 2005 International Conference on Hardware/Software Codesign and System Synthesis (CODES-05), pp 273-278, September 2005
  6. An FPGA based soft multiprocessor system for IPv4 packet forwarding, Kaushik Ravindran, Nadathur Satish, Yujia Jin and Kurt Keutzer, Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL 2005), pp 487-492, August 2005