Homework #2

                Our searching is focused on application specific components and building blocks for communication applications.
 

Convolutional codes are widely used to encode digital data before transmission through noisy or error-prone channels. During encoding, k input bits are mapped to n output bits to give a rate k/n coded bitstream. The encoder consists of a shift register of kL stages, where L is described as the constraint length of the code.

At the receiver, the bitstream can be decoded to recover the original data, correcting errors in the process. The optimum decoding method is maximum-likelihood decoding where the decoder attempts to find the closest "valid" sequence to the received bitstream. The most popular algorithm for maximum-likelihood decoding is the Viterbi Algorithm. The possible received bit sequences form a "trellis" structure and the Viterbi Algorithm tracks likely paths through the trellis before choosing the most likely path.

Description:

Performs a real-time, fixed latency, maximal-likelihood detection of 1-bit information encoded with an n-bit convolutional code.

Major programmable parameters:

chain-back depth
constraint length
encoder generating functions
code wordlength
soft decision wordlenggth
accumulated state metric wordlength

Performance:

Specification:

Constraint length 7, rate 1/2 encoder/decoder
48 states chainback depth
3-bit soft-decision decoder inputs

Perfomance (synthesized to a 0.5um CMOS process, norminal conditions):
 

	Area Optimized	Spped-Area Balanced	Speed Optimized
# ACS Units	1	8	64
Speed (Msps)	0.810	6.32	85
Gates	3,200	19,400	34,900

Use Model:

Parameterized synthesizeable soft core

Reference:

http://www.mentor.com/eparts/webdocs/site/products/datasheets/index.html

Description:

Similar function as above, which provides hard- or soft-decision decoding (soft-decision decoding gives better error correction performance at the expense of more processing). Many options can be supported including variable constraint length, variable rate and punctured codes.

Performance:
 
Memory, speed and interface can be customized.
Use Model:

Hardware:

Fully simulated, synthesizable RTL Verilog or VHDL core together with Verilog or VHDL test bench, optional C or C++ implementation for verification purposes, full documentation and test results.

Software:

Fully tested C or C++ implementation with test program, full documentation and test results.

Support options include: email and telephone support for 6 or 12 months, on-site visits, design integration assistance, simulation studies.

Price depends on license requirements. Flexible license options available include:

one-off license payment (allows royalty-free redistribution and resale for one product/product line)
per-unit license payment (royalty payments on each unit redistributed or resold).

Reference:

http://www.4i2i.com/viterbi.htm

Description:

Reed-Solomon codes are block-based error correcting codes with a wide range of applications including:
            Error correction for storage devices (e.g. Compact Disk, DVD, etc) and for barcodes
            Mobile and personal communications
            Digital communications in noise-prone environments

The RSEncoder function takes an array of k data symbols as an input and returns an array of n symbols (a Reed-Solomon codeword), which can correct up to t=(n-k)/2 symbol errors.

The RSDecoder function takes as its input a received codeword of n symbols and returns k decoded data symbols, together with a count of the number of symbol errors corrected (or a flag indicating that more than t errors were present).

Reed-Solomon RS(255,255-2t) code with 8-bit symbols (other codeword or symbol sizes can be generated if required)
Codeword may be shortened to (s, s-2t) where s < 255
Parity overhead is 2t symbols (bytes) per codeword
Corrects up to t symbol errors anywhere in a codeword

Performance:
 
Gate count and clock speed depend on the exact R-S code and on the required encode/decode rate, for example:
            Low gate count can be achieved at expense of higher clock speed and/or latency
            Higher clock speed/low latency can be achieved at expense of higher gate count
 

Code	Gate Count	Clock Cycles per Codeword
(255, 249)	7,000	700
(255, 239)	11,000	2,000
(204, 188)	11,000	2,000
(255, 223)	17,000	6,000

Use Model:

 Complete package includes:
            Fully simulated, synthesizable RTL Verilog or VHDL core
            Verilog or VHDL test bench and test vectors or test program
            C or C++ implementation of same RS code for verification purposes
            Full documentation
            12 months warranty and email/telephone support

Licensing options include:
            one-off license payment
            per-unit license payment

Reference:

http://www.4i2i.com/reed_solomon_ip_cores.htm

Description:

Same as above.

Performance:
 
Performance depends on a number of factors. In general, more processing is required for larger values of t (number of correctable symbols). The following table shows approximate worst-case data rates on a 166MHz Pentium (encoding and decoding, correcting the maximum t errors every code word).
 

Code	Data Rate
RS (255, 251)	12 Mbps
RS (255, 239)	2.72 Mbps
RS (255, 223)	1.17 Mbps

Use Model:

Complete package includes:
            C or C++ implementation of RS code, optimized for speed, memory and/or platform
            Software testbench
            Full documentation including functional description, module descriptions, test procedures and test results
            Comprehensive warranty and support (many options available including email support, telephone support and site visits)

Licensing options include:
            Single-user license
            Redistribution license (one license fee paid on delivery of package)
            Redistribution license (per-unit royalty payment)

Reference:

http://www.4i2i.com/reed_solomon_software.htm

Description:

Similar functions as above.

Major programmable parameters:

symbol wordlength
Galois Field primitive polynomial coefficients
Maximum number of correctable symbols in a N symbol code word

Performance:
 
 

(n, k, t)	Configuration	Speed (nom. 0.5um)	Gate Count (2-in NAND)
(255, 239, 8)	fixed	78 Msps	2683
(255, 239, 8)	programmable (t=1 ... 8)	94 Msps	5428
(255, 239, 8)	programmable with interleaving support	93 Msps	5788

Use Model:

Parameterized synthesizeable soft core

Reference:

http://www.mentor.com/eparts/webdocs/site/products/datasheets/index.html

Description:

A real-time continous block decoding operation (BCH) of an N word block of log2(N+1) bit symbols containing K=N-2t words of information (code rate=K/N).

Major programmable parameters:

block length
code rate
correction capability

Performance:
 
Based on a 0.5um (nom) technology.

	N=127, t=4	N=255, t=4	N=255, t=8
Speed	52MHz (7-bit sps)	44MHz (8-bit sps)	48.5MHz (8-bit sps)
Gates (not including ROM ot RAM)	9,315	9,530	18,855

Use Model:

Parameterized synthesizeable soft core

Reference:

http://www.mentor.com/eparts/webdocs/site/products/datasheets/index.html

Description:

A complete, fully digital implementation of the symbol mapping, pulse shape filtering, complex to real up comversion, and programmable IF/RF modulation functions. Standard configurations with parameter values pre-set to meet commercial stardards such as ITU-T J.83, DVB, MCNS, IEEE 802.14, IESS 308, ect. are available.

Major programmable parameters:

Pulse shaping filter coefficients
signal constellations
symbol rates

Performance:



Use Model:

Parameterized synthesizeable soft core
Multiple speed-area solutions available for any given functional specification
Behavioral models including C model and bit-true, cycle-based model

Reference:

http://www.mentor.com/eparts/webdocs/site/products/datasheets/index.html

Description:

A complete, fully digital IF sampled QAM receiver, which performs phase splitting, adaptive channel equalization, matched filtering, carrier recovery, symbol timing recovery, AGC control and QAM de-mapping. Standard configurations with parameter values pre-set to meet commercial stardards such as ITU-T J.83, DVB, MCNS, IEEE 802.14, DAVIC, ect. are available.

Major programmable parameters:

constellation size
QAM/QPSK mapping table
PLL gain
LMS adaptation loop step size
adaptation modes

Performance:



Use Model:

Parameterized synthesizeable soft core
Behavioral models including C model and bit-true, cycle-based model

Reference:

http://www.mentor.com/eparts/webdocs/site/products/datasheets/index.html

Similar description as above.

Use Model:
 

Hardware:
VHDL or Verilog cores which are suitable for synthesis to ASIC or FPGA.
Software:
Implementations are highly optimised for speed and/or size and are suitable for a wide range of platforms including PC and DSP processors.
Reference:

http://www.4i2i.com/products.htm

Description:
The core performs a direct form linear phase FIR filter operation. The core can be implemeted with fixed or programmable coefficeints to achieve the best performance.
Performance/Power/Cost:
Performance on based on the parameters.

Use Model:
This core is delivered as a parameterizable soft core. Parameters can be set to get the best performace (for example, fixed or prgrammable coefficients, degree of resource sharing and pipelining etc.) Detailed documentation on the parameters and interface behavior is in the literature which can be found at the referenced web site.

http://www.mentor.com/eparts/webdocs/site/products/datasheets/index.html

            This is a flexible core designed to implement any of the following three functions:  FFT/IFFT, a windowed FFT or a merged FFT-Spectral Multiply-IFFT fast convolution.

This is a parameterized synthesizable soft core. Parameters (including number of fft points, bit width etc.) and I/O behavior (I/O port descriptions) is detailed in the literature.

A core that implementes the 8x8 2-D discrete cosine transform and inverse discret cosine transform. DCT/IDCT are essential components of many digital image coding systmes including JPEG, MPEG-1, MPEG-2, H.261 and H.263.

From [1]

    Use Model:

From [1]:
 A synthesizable core is delivered. The inputs are the 8x8 pixels in left-to-right, top-to-bottom order. The ouputs can be in row scanned order or zig-zag order, dependeing on the parameter. Parameters and interfaces are documented in detail in the literature.
From [3]:
 The complete IP package includes:
•   Fully simulated, synthesizable soft RTL Verilog or VHDL core
•   Verilog or VHDL test bench and test vectors or test program
•    C or C++ implementation for verification purposes
•    Full documentation
•    12 months warranty and email/telephone support
Interface and parameters are specifed in the documentation which can be found on the web site. The company can also change the interface to customized other needs.
 

Description:
This core provides a all digital phase locked loop (PLL) function. PLLs are widely used in the telecommunication applications for data and clock recovery and synchronization. The structure of the PLL is shown below.

Performance/Power/Cost:
Maximum of 10ns jitter at 50MHz. Infinite frequency hold time and programma$ center frequency.

Use Model:
            &nb$ This is a parameterizable soft core delivering
• Synthesisable  VHDL model
• Fully synchronous design
• Adaptable phase detector
• Scalable oscillator and loop filter
•  Customizable for special requirements

Description:
 UTOPIA is a standard for ATM interfaces defined by the ATM-Forum. The core [2] provided is Level I/II compliant and compsed of two units (one transmitter and one receiver). Each units can be configured to be in Master or Slave mode. Other configurable parameters include frame length and data bus width.
Performance/Power/Cost:
It is capable of supporting 25/33/50 MHz.
Estimated gate count: 10K [1].

Use Model:
This is a parameterizable soft core including:
• Structured synchronous design
• Synthesizable VHDL description
• Flexible custom interface
• Management Interface

Description:
This transceiver core is designed to interface programmable and standard logic with the USB. Applications include human interface devices and compute telephony systems.

Performance/Power/Cost:

The core is capable of support full speed at 12Mbits/sec as well as low speed at 1.5Mbits/sec. The core is silicon proven at 0.8 um CMOS technology and the correspondng die size is  1.2 mm².

Use Model:

It's is a hard core wchich can be ported to users's layout library. The company claims to rapidly port the core to 0.5,0.35 or 0.25 micro technology. The deliverables of the core are

• GDSII Layout and corresponding Schematic Netlist
• Simulated, Ported and Verified to your process technology.
• Detailed Documentation.

Note:

The same company also provides ADC (Analog-to-Digital converters) as hard cores but no detailed documentations are available online.

Currently, there are not many application specific IP block providers, especially for large blocks such as MPEG. So we focus on searching for smaller building blocks for communication applications.
Many commonly used communication building blocks are available as IP blocks using different use models, which is very helpful for system-on-chip development.  The most popular use model we found is parameterizable soft cores which suggest that synthesis will be a major part of component-based-design.
Performance, power, and cost numbers heavily depend on programmable parameter values and implementation technology that the IP users are targetting. There are not many documentations on power and cost from the IP vendor. Therefore, more detailed information will be very helpful for future usage of such IPs.

References: