Louis P. Alarcón's Webpage
Louis P. Alarcón's Webpage
I'm a graduate student pursuing a PhD in Electrical Engineering and Computer Science
(EECS) at the
University of California, Berkeley.
I'm currently working on integrated circuits for
ultra-low energy computation at the Berkeley Wireless Research Center
(BWRC)
and my advisor is Professor Jan M. Rabaey.
Before coming to Berkeley, I received my BS and MS degrees in
Electrical Engineering from the
University of the Philippines, Diliman.
Advisor: Professor Jan M. Rabaey
The SAPTL is an alternative circuit topology that allows the reduction of energy per operation via voltage scaling even in the presence of leakage. It allows aggressive threshold voltage scaling since the Vth of the stack transistors can now be decoupled with its subthreshold leakage, enabling the use of very low threshold voltages and thus allowing the stack transistors to remain in the superthreshold region. In addition, the differential signaling used by the SAPTL lends itself to synchronous and asynchronous operation and the inherent layout regularity points to the SAPTL as a very good candidate for robust ultra low energy operation.
L. Alarcón, T.-T. Liu, M. Pierson, and J. Rabaey,
"Exploring Very Low-energy Logic: A Case Study", Journal of Low Power Electronics,
vol. 3, no. 3, pp. 223–233, Dec. 2007
T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey,
"Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic",
Proceedings of International Symposium on Asynchronous Circuits and Systems (ASYNC), 2008
Liu, T.-T., Alarcón, L. P., Pierson, M. D., Rabaey, J. M.,
"Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic",
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on,
vol.17, no.7, pp. 883-892, July 2009
Berkeley Wireless Research Center (BWRC)
2108 Allston Way Suite 200, Berkeley, CA
Phone: +1 510 666 3142
Email: lalarcon at eecs dot berkeley dot edu
Last updated: June 28, 2009