Research Areas

Kuh's Group Publications

  1. Hsu, Chi-Ping, "A New Two-Dimensional Routing Algorithm," Proc. IEEE 19th Design Automation Conference, pp. 46 - 50, 1982. [NSF, Bell]

  2. Takahashi, M. and C.P. Hsu, "gerk l.5 M.," November 1982.

  3. Takahashi, M. and C.P. Hsu, "gerk 2 M.," November 1982.

  4. Hsu, C.P., "General River Routing Algorithm," Proc. IEEE 20th Design Automation Conference, pp. 578 - 582, June 1983. [NSF, AFOSR, JSEP, Bell]

  5. Chen, Nang-Ping, "New Algorithms for Steiner Tree on Graphs," Proc 1983 ISCAS, pp. 1217 - 1219, May 1983. [NSF, AFSC]

  6. Li, Jeong-Tyng, "Algorithms for Gate Matrix Layout," Proc. 1983 IEEE ISCAS, pp. 1013 - 1016, May 1983. [NSF]

  7. Takahashi, M. and C.P. Hsu, "General River Router," Proc. 1983 IEEE ISCAS, pp. 1233 - 1236, May 1983. [NSF, AFOSR]

  8. Hsu, Chi-Ping, "Minimum-Via Topological Routing," IEEE Trans. CAD, vol. CAD-2, no. 4, pp. 235 - 256, October 1983. [AFOSR, NSF, JSEP, Bell]

  9. Marek-Sadowska, Malgorzata and Tom Tsan-Kuo Tarng, "Single-Layer Routing for VLSI: Analysis and Algorithms," IEEE Trans. on CAD, vol. CAD-2, no. 4, pp. 246 - 259, October 1983. [NSF, MICRO]

  10. Sadowska, M.M. and J.T. Li, "Global Router for Gate Array," IEEE ICCAD 83, pp. 131 - 132, September 1983. [NSF, MICRO]

  11. Chen, Yun Kang and Mei Lun Liu "Three-Layer Channel Routing," IEEE Trans. on CAD, vol. CAD-3, no. 2, April 1984. [NSF]

  12. Marek-Sadowska, M., "An Unconstrained Topological Via Minimization Problem for Two-Layer Routing," IEEE Trans. on CAD, vol. CAD-3, no. 3, pp. 184-190, July 1984. [NSF, MICRO]

  13. Li, Jeong-Tyng and M. Marek-Sadowska, "Global Routing for Gate-Array," IEEE Trans. on CAD, vol. CAD-3, no. 4, pp. 298-307, October 1984. [Bell]

  14. Marek-Sadowska, M., "Global Router For Gate Array," Conf. Proc. of ICCD '84, Portchester, New York pp. 332-337, October 1984. [NSF, MICRO]

  15. Marek-Sadowska, Malgorzata, "Two-Dimensional Router For Double Layer Layout," IEEE 22nd Design Automation Conference, pp. 117-123, June, 1985. [NSF]

  16. Asano, Tetsuo, "An Efficient Algorithm for Computing the Reachability Polygon from a Point: Rectilinear Case," Proceedings of ISCAS 1985, pp. 1293-1296, June 1985. [NSF]

  17. Cheng, Chung-Kuan, "Decomposition Algorithms for Linear Placement and Applications to VLSI Design," Proceedings of ISCAS 1985, pp. 1047-1050, June 1985. [NSF, Hughes]

  18. Dai, Wei-ming and Tetsuo Asano, "A New Routing Region Definition and Ordering Scheme Using," L-Shaped Channels," Proceedings of ISCAS 1985, pp. 29-30, June 1985. [Bell, SRC, NSF]

  19. Asano, Tetsuo "An Efficient Algorithm for Finding the Visibility Polygon for a Polygonal Region with Holes," Transactions of the IECE of Japan, vol. E-68, no. 9, pp. 557-559, September 1985. [NSF] (no copy in files)

  20. Asano, Tetsuo "An Efficient Algorithm for Finding the Region Reachable within k Bends," Transactions of the IECE of Japan, vol. E-68, no. 12, pp. 831-835, December 1985. (no copy in files)

  21. Xiong, J.G., "Algorithms for Global Routing," Proc. of 23rd Design Automation Conference, pp. 824-830, July 1986. [NSF/INT]

  22. Chen, Howard H., "Trigger: A Three-Layer Gridless Channel Router," Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pp. 196-199, November 1986. [SRC]

  23. Marek-Sadowska, Malgorzata, "Route Planner for Custom Chip Design," Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pp. 246-249, November 1986. [NSF, MICRO]

  24. Xiong, J.G., "A Gridless Maze Router: DBM (Diffraction Boundary Method," Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pp. 192-195, November 1986. [NSF]

  25. Xiong, Xiao-Ming, "Nutcracker: An Intelligent Channel Spacer," presented at International Workshop on Symbolic Layout and Compaction, November 1986. [SRC]

  26. Sato, Masao, "An Optimal Algorithm for Finding Minimum Space/Width of Rectilinear Regions," Bulletin of the Centre for Informatics, Waseda University, vol. 5, pp. 1-15, Spring 1987. [NSF, MICRO]

  27. Sato, Masao and Tatsuo Ohtsuki, "Enhanced Plane-Sweep Method for LSI Pattern Design Problems," Proceedings of Japan Circuits and Systems Conference, pp. 87-94, 1987. [NSF, MICRO]

  28. Sato, Masao, Jiro Sakanaka, and Tatsuo Ohtsuki, "A Fast Line-Search Method Based on a Tile Plane," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 588-591, May 1987. [NSF, MICRO]

  29. Chen, Howard H., "Routing L-Shaped Channels in Nonslicing-Structure Placement," Proceedings of 24th ACM/IEEE Design Automation Conference, pp. 152-158, June 1987. [SRC, NSF, MICRO]

  30. Agrawal, Vishwani D., and Kwang-Ting Cheng, "Threshold-Value Simulation and Test Generation," NATO Avanced Study Institute on Testing and Diagnosis of VLSI and ULSI, June 1987.

  31. Marek-Sadowska, Malgorzata, "Pad Assignment for Power Nets in VLSI Circuits," IEEE Transactions on Computer-Aided Design, vol. CAD-6, no. 4, pp. 550-560, July 1987.

  32. Agrawal, Vishwani D., Kwang-Ting Cheng, Daniel D. Johnson, and Tonysheng Lin, "A Complete Solution to the Partial Scan Problem," Proceedings of the International Test Conference, pp. 44-51, September 1987. [NSF, MICRO]

  33. Cheng, Kwang-Ting and Vishwani D. Agrawal, "A Simulation-Based Directed-Search Method for Test Generation," Proceedins of the IEEE International Conference on Computer Design: VLSI in Computers and Processors," pp. 48-51 October 1987. [NSF, MICRO]

  34. Cheng, Kwang-Ting, Vishwani D. Agrawal, and Prathima Agrawal, "Use of A Concurrent Fault Simulator for Test Vector Generation," Proceedings of AT&T Conference on Electronic Testing, October 1987.

  35. Agrawal, Vishwani D., Kwang-Ting Cheng, Daniel D. Johnson, and Tonysheng Lin, "Designing Circuits with Partial Scan," IEEE Design and Test of Computers, pp. 8-15, April 1988. [NSF, MICRO]

  36. Daijavad, S., E. Polak, and R-S. Tsay, "A Combined Deterministic and Random Optimization Algorithm for the Placement of Macro-Cells," Proceedings of International Workshop on Placement and Routing, May 1988. [NSF, MICRO]

  37. Agrawal, Vishwani D., Kwang-Ting Cheng, and Prathima Agrawal, "Contest: A Concurrent Test Generator For Sequential Circuits," Proceedings of 25th Design Automation Conference, pp. 84-89, June 1988.

  38. Xiong, Xiao-Ming, "A New Algorithm for Topological Routing and Via Minimization," Digest of Technical Papers, International Conference on Computer-Aided Design, pp. 410-413, November 1988. [SRC]

  39. Makedon, Fillia and Malgorzata Marek-Sadowska, "Analysis of Heuristic Reasoning for the Visualization of CAD Heuristics," Lecture Notes in Computer Science, 2nd Int. Conf. on Computer-Aided Learning, pp. 359-378, May 1989. [MICRO, NSF]

  40. Srinivasan, Arvind, "Mole -- A New Template Based Router," UCB/ERL Memo M89/58, May 1989. [JSEP, NSF]

  41. Dutta, Robi and Malgorzata Marek-Sadowska, "Automatic Sizing of Power/Ground (P/G) Networks in VLSI," Proceedings of 26th Design Automation Conference, pp. 783-786, June 1989. [MICRO, NSF]

  42. Pedram, Massoud, "Automatic Layout of Silicon-on-Silicon Hybrid Packages," UCB/ERL Memo M89/80, June 1989. [SRC, NSF]

  43. Preas, Bryan, Massoud Pedram, and Don Curry, "Automatic Layout of Silicon-on-Silicon Hybrid Packages," Proceedings of 26th Design Automation Conference, pp. 394-399, June 1989. [SRC, NSF]

  44. Xu, Dong-Min, "GM: A New Gate Matrix Layout System," UCB/ERL Memo No. M89/81, June 1989. [NSF]

  45. Pedram, Massoud, and Bryan Preas, "Accurate Prediction of Physical Design Characteristics for Random Logic," Proceedings of ICCD, pp. 100-108, October 1989. [SRC, NSF]

  46. Marek-Sadowska, Malgorzata, and Shen P. Lin, "Timing Driven Placement," Digest of Technical Papers, Int. Conf. on Computer-Aided Design, pp. 94-97, November 1989. [MICRO, NSF]

  47. Parng, Tai-Ming, and Ren-Song Tsay, "A New Approach to Sea-of-Gates Global Routing," Digest of Technical Papers, Int. Conf. on Computer-Aided Design, pp. 52-55, November 1989. [NSF, JSEP]

  48. Pedram, Massoud, and Bryan Preas, "Interconnection Length Estimation for Optimized Standard Cell Layouts," Digest of Technical Papers, Int. Conf. on Computer-Aided Design, pp. 390-393, November 1989. [SRC]

  49. Lin, Shen P. and Malgorzata Marek-Sadowska, "An Accurate and Efficient Delay Model for CMOS Gates in Switch-Level Timing Analysis," Proceedings of International Symposium on Circuits and Systems, pp. 856-860, May 1990. [NSF, MICRO]

  50. Pedram, Massoud, Wayne Wei-Ming Dai, Malgorzata Marek-Sadowska, and Yasushi Ogawa, "Ongoing Research and Development of BEAR Layout System," Proceedings of MCNC International Layout Synthesis Workshop, pp. 1-17, May 1990. [SRC, NSF, MICRO]

  51. Wang, Deborah, "Pad Placement and Ring Routing for Custom Chip Layout," Proceedings of 27th Design Automation Conference, pp. 193-199, June 1990. [SRC]

  52. Xu, Dong-Min, "Cell Generation and Two-Dimensional Folding for VLSI Layout," UC Berkeley Electronics Research Laboratory Memo No. UCB/ERL M90/52, June 12, 1990. [NSF]

  53. Pedram, Massoud and Bryan Preas, "A Hierarchical Floorplanning Approach," Proceedings of International Conference on Computer Design, pp. 332-338, September 1990.

  54. Marek-Sadowska, Malgorzata and Shen P. Lin, "Pin Assignment for Improved Performance in Standard Cell Design," Proceedings of International Conference on Computer Design, pp. 339-342, September 1990. [NSF, MICRO]

  55. Srinivasan, Arvind, Sridhar Seshadri, and J. George Shanthikumar, "Stochastic Cycle Time Optimization of Sequential Systems," UC Berkeley Electronics Research Lab. Memo No. M90/91, October 1990.

  56. Pedram, Massoud, Narasimha Bhat, and Kamal Chaudhary, "Layout-Oriented Technology Mapping and IO Pad Assignment,| UC Berkeley Electronics Research Lab. Memo No. M90/97, November 1990. [SRC]

  57. Srinivasan, Arvind, "A Dual Quadratic Programming Algorithm for Performance-Driven Placement," UC Berkeley Electronics Research Lab. Memo No. M90/107, November 1990. [SRC]

  58. Srinivasan, Arvind, Timothy Kam, Sharad Malik, and Robert K. Brayton, "Algorithms for Discrete Function Manipulation," Digest of Technical Papers, Int. Conf. on Computer-Aided Design, pp. 92-95, November 1990. [NSF, SRC]

  59. Mayrhofer, S., M. Pedram, and U. Lauther, "A Flow-Based Approach to the Placement of Boolean Networks," Proc. VLSI, 1991.

  60. Lin, Shen, and Malgorzata Marek-Sadowska, "A Fast and Efficient Algorithm for Determining Fanout Trees in Large Networks," pp. 539-544, Proc. European Design Automation Conference, February 1991. [NSF, MICRO]

  61. Srinivasan, Arvind and D.P. LaPotin, "Cycle Time Optimization Subject to Packaging Constraints," pp. 40-52, Proc. Multi-Chip Modules Workshop, UC Santa Cruz, March 1991.

  62. Pedram, Massoud and Narasimha Bhat, "Layout Driven Technology Mapping," Proc. 28th Design Automation Conference, pp. 99-105, June 1991. [NSF, SRC]

  63. Srinivasan, Arvind, "An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs," Proc. 28th Design Automation Conference, pp. 636-639, June 1991. [SRC]

  64. Wang, Deborah, "Novel Routing Schemes for IC Layout. Part I: Two-Layer Channel Routing," Proc. 28th Design Automation Conference, pp. 49-53, June 1991. [SRC]

  65. Pedram, M., "An Integrated Approach to Logic Synthesis and Physical Design," Ph.D. Thesis, UCB/ERL Memorandum M91/69, August 1991.

  66. Pedram, M., and N. Bhat, "Layout Driven Logic Decomposition/Restructuring," Proc. ICCAD, pp. 134-137, November 1991. [SRC, NSF]

  67. Srinivasan, A., "Performance Optimization of Large-Scale Integrated Circuits," Ph.D. thesis, UCB/ERL Memorandum M91/104, November 1991. [SRC]

  68. Chaudhary, Kamal, and Massoud Pedram, "A Near Optimal Algorithm for Technology Mapping Minimizing Area Under Delay Constraints," Proc. Design Automation Conference, pp. 492-498, 1992 [NSF, DARPA]

  69. Bhat, Narasimha B., "A New Library-Based Performance-Driven Mapper for LUT FPGAs," Extended Abstract Volume, SRC Techcon '93, pp. 117-119, September 1993.

  70. Liu, Lung-Tien, Minshine Shih, Nan-Chi-Chou, Chung-Kuan Cheng, and Walter Ku, "Performance-Driven Partitioning Using Retiming and Replication," Digest of Technical Papers, IEEE/ACM Int. Conf. on CAD, pp. 296-299, November 1993.

  71. * Hu, Rongxiang, "Integrating Networks Characterized by Measured S-Parameter Data into SWEC," UCB/ERL Memorandum M94/68, August 1994.

  72. Lung-Tien Liu, Minshine Shih, and Chung-Kuan Cheng, "Data Flow Partitioning for Clock Period and Latency Minimization," 31st Design Automation Conference, pp. 658-663, June 1994.

  73. Esbensen, H., "Computer Near-Optimal Solutions to the Steiner Problem in a Graph Using a Genetic Algorithm," Networks, Vol. 26, pp. 173-185, 1995.

  74. Esbensen, H., "Finding (Near-)Optimal Steiner Trees in Large Graphs," Proceedings of the Sixth International Conference on Genetic Algorithms, pp. 485-491, 1995.

  75. Esbensen, H., "Defining Solution Set Quality," UCB/ERL Memorandum M 96/1, January 1996.

Back to top

Last updated 03/19/07