PUBLICATIONS
E.S. Kuh  Publications
Books

Kuh, E.S. and D.O. Pederson, Principles of Circuit Synthesis, McGrawHill,
New York, 1959, 244 pages.

Kuh, E.S. and R.A. Rohrer, Theory of Linear Active Networks, HoldenDay,
Inc., San Francisco, CA, 1967, 650 pages.

Desoer, C.A., and E.S. Kuh, Basic Circuit Theory, McGrawHill, New
York, 1969, 876 pages. Italian translation, 1972. Chinese translation,
1972. Russian translation, 1976. Japanese translation, 1977. Portuguese
translation, 1979. PRC translation, 1979.

Chua, L.O., C.A. Desoer, and E.S. Kuh, Linear and Nonlinear Circuits,
McGraw Hill, New York, 1987, 839 pages.

Kuh, E.S., editor, Multichip Modules, World Scientific, Singapore,
1992, 145 pages.

Hu, T.C., and E.S. Kuh, eds., VLSI: Circuit Layout Theory and Techniques,
IEEE
Press, October 1985.
Papers
1950  1959 / 1960  1969 /
1970
 1979 / 1980  1989 / 1990  1999
/ 2000  present

Kuh, E.S., "Potential Analog Network Synthesis for Arbitrary
Loss Functions," J. of Applied Physics, vol. 24, no. 7, pp. 897902,
July 1953.

Kuh, E.S., "Parallel Ladder Realization of Transfer Admittance Functions,"
Proc.
of the Natl. Electronics Conf., vol. 10, pp. 198206, October 1954.

Kuh, E.S., "Special Synthesis Techniques for Driving Point Impedance Functions,"
IRE
Trans. on Circuit Theory, CT2, no. 4, pp. 302308, December 1955.

Kuh, E.S., Review of "Elementary Operations which Generate Network Matrices,"
by R.J. Dufflin, Am. Math. Soc. Trans., June 1955; published in
IRE
Trans. on Circuit Theory, CT3, no. 2, p. 152, June 1956.

Kuh, E.S., "Synthesis of Lumped Parameter Decision Delay Line," Proc.
of the IRE, vol. 45, no. 112, pp. 16321642, December 1957.

Kuh, E.S., Review of Network Synthesis, by N. Balabanian, Prentice
Hall, 1958; published in Proc. of the IRE, vol. 46, no. 2, p. 348,
February 1958.

Kuh, E.S., "Synthesis of RC Grounded TwoPorts," IRE Trans. on Circuit
Theory, CT5, no. 1, pp. 5561, March 1958.
19601969

Paige, A., and E.S. Kuh, "Maximum Gain Realization of an RC Ladder Network,"
IRE
Trans. on Circuit Theory, CT7, pp. 3240, March 1960.

Kuh, E.S., "Regenerative Modes of Active Networks," IRE Trans. on Circuit
Theory, CT7, pp. 6263, March 1960.

Desoer, C.A., and E.S. Kuh, "Bounds on Natural Frequencies of Linear Active
Networks," Proc. of Active Networks and Feedback Systems, Polytechnic
Institute of Brooklyn, pp. 415436, April 1960.

Kuh, E.S., Review of Laplace Transforms for Electronic Engineers,
by J.G. Holbrook, Pergamon Press, 1959; published in Proc. of the IRE,
vol. 48, no. 7, p. 1350, July 1960.

Kuh, E.S., "Voltage Transfer Function Synthesis of Active RC Networks,"
IRE
Trans. on Circuit Theory, CT7, pp. 134138, August 1960.

Kuh, E.S., and J.D. Patterson, "Design Theory of Optimum NegativeResistance
Amplifiers," Proc. of the IRE, vol. 49, no. 6, pp. 10431050, June
1961.

Kuh, E.S., and M. Fukada, "Optimum Synthesis of WideBand Parametric Amplifiers
and Convertors," IRE Trans. on Circuit Theory, CT8, pp. 410415,
December 1961.

Kuh, E.S., "Theory and Design of WideBand Parametric Convertors," Proc.
of the IRE, vol. 50, no. 1, pp. 3138, January 1962.

Kuh, E.S., Network Theory: "Generalized Equations and Topological Analysis,"
The
Encyclopedia of Electronics, pp. 524526, Reinhold Publishing Corp.,
1962.

Kuh, E.S., "Some Results in Linear Multiple Loop Feedback Systems," Proc.
of the Allerton Conf. on Circuit and Systems Theory, vol. 1, pp. 471483,
November 1963.

Kuh, E.S., "TimeVarying Networks  the State Variable, Stability and
Energy Bounds," The Inst. of Electronics and Communications Engineers
of Japan, ICMCI Summary, Part II, pp. 9192, 1964.

Kuh, E.S., and R.A. Rohrer, "The StateVariable Approach to Network Analysis,"
Proc.
of the IEEE, vol. 53, no. 7, pp. 672686, July 1965.

Kuh, E.S., "Stability of Linear TimeVarying Networks  The State Space
Approach," IEEE Trans. on Circuit Theory, CT12, no. 2, pp. 150157,
June 1965.

Kuh, E.S., Review of Circuits with Periodically Varying Parameters,
by D.G. Tucker, Van Nostrand, 1965; published in Proc. of the IEEE,
vol. 53, no. 8, pp. 11661167, August 1965.

Biswas, R.N., and E.S. Kuh, "Multiparameter Sensitivity Analysis for Linear
Systems," Proc. of the Allerton Conf. on Circuit and System Theory,
vol. 3, pp. 384393, October 1965.

Kuh, E.S., "Representation of Nonlinear Networks," Proc. of the Natl.
Electronics Conference, vol. 21, pp. 702707, October 1965.

Chan, T.Y., and E.S. Kuh, "A General Matching Theory and Its Application
to Tunnel Diode Amplifiers," IEEE Trans. on Circuit Theory, CT3,
no. 1, pp. 618, March 1966.

Kuh, E.S., "Nonlinear and TimeVariable Networks," Acta Polytechnica,
Prace Cvut, V. Praze, vol. IV, no. 1, pp. 8798, 1966.

Kuh, E.S., D.M. Layton, and J. Tow, "Network Analysis and Synthesis Via
State Variables," ERL/UCB Memorandum M169, July 1966.

Kuh, E.S., D.M. Layton, and J. Tow, "Network Analysis and Synthesis via
State Variables," in Network and Switching Theory, Academic Press,
N.Y., 1968.

Kuh, E.S., "A MinimumSensitivity MultipleLoop Feedback Design," Proc.
of the Hawaii Internatl. Conf. on System Science, pp. 5356, 1968.

Biswas, R.N., and E.S. Kuh, "Multiple Loop Feedback Synthesis and Sensitivity
Optimization," Proc. of the Circuit Theory Conf., Prague, Czechoslovakia,
pp. 115, July 1968.

Kuh, E.S., and C.G. Lau, "Sensitivity Invariants of Continuously Equivalent
Networks," IEEE Trans. on Circuit Theory, CT15, no. 3, pp. 175177,
September 1968.

Kuh, E.S., "State Variables and Feedback Theory," IEEE Trans. on Circuit
Theory, CT16, no. 1, pp. 2326, February 1969.

Kuh, E.S., "Progress in Radio Waves and Transmission of Information: Information
Theory, Circuit Theory and ComputerAided Design," Radio Science,
vol. 4, no. 7, pp. 651656, July 1969.
1970  1979

Desoer, C.A., and E.S. Kuh, "Teaching Basic Circuit Theory for the 1970's,"
in ects of Network and System Theory, eds., R.E. Kalman and N. DeClaris,
Holt, Rinehart and Winston, pp. 627639, 1971.

Kuh, E.S., and I.N. Hajj, "Nonlinear Circuit Theory: Resistive Networks,"
Proc.
of the IEEE, vol. 59, no. 3, pp. 340355, March 1971.

Kuh, E.S., "Circuits, Feedback and Dynamical Systems," Japanese J. of
Systems and Control, vol. 15, no. 3, pp. 204211, 1971.

Fujisawa, T., and E.S. Kuh, "PiecewiseLinear Theory of Nonlinear Resistive
Networks," Internatl. Conf. on Systems, Networks and Computers,
Oaxtepec, Mexico, pp. 112113, January 1971.

Fujisawa, T., and E.S. Kuh, "Some Results on Existence and Uniqueness of
Solutions of Nonlinear Networks," IEEE Trans. on Circuit Theory,
CT18, no. 5, pp. 501506, September 1971.

Kuh, E.S., Dertouzos, Bashkow, Carlin, Rowe, Smullin and Van Valkenburg,
"Insights vs. Algorithms: A Leader's View," IEEE Trans. on Education,
E14, no. 4, pp. 164169, November 1971.

Biswas, R.N., and E.S. Kuh, "Optimum Synthesis of a Class of MultipleLoop
Feedback Systems," IEEE Trans. on Circuit Theory, CT18, no. 6,
pp. 582587, November 1971.

Biswas, R.N., and E.S. Kuh, "A Multiparameter Sensitivity Measure for Linear
Systems," IEEE Trans. on Circuit Theory, CT18, no. 6, pp. 718719,
November 1971.

Kuh, E.S., and H. Abed, "Invertability, Reproducibility and Decoupling
of a Class of Nonlinear Systems," IEEE Decision and Control Conf.,
pp. 6168, December 1971.

Fujisawa, T., and E.S. Kuh, "PiecewiseLinear Theory of Nonlinear Networks,"
SIAM
J. on Applied Mathematics, vol. no. 2, pp. 307328, March 1972.

Fujisawa, T., E.S. Kuh, and T. Ohtsuki, "A Sparse Matrix Method for Analysis
of PiecewiseLinear Resistive Networks," IEEE Trans. on Circuit Theory,
CT19, no. 6, pp. 571584, November 1972.

Kuh, E.S., "Sparse Matrix Method for Analysis of Large Networks," in Network
and Signal Theory, (J.K. Skwirzynski and J.O. Scanlon, Peter Peregrinus
Ltd., London), pp. 119121, 1972.

Cheung, L.K., and E.S. Kuh, "A GraphTheoretic Method for Optimal Partitioning
of Large Sparse Matrices," Proc. 6th Hawaii Internatl. Conf. on System
Sciences (second supplement), pp. 4548, 1973.

Kuh, E.S., "Partitioning and Tearing of Large Scale Systems," Proceedings
4th Pittsburgh. Conf. on Modeling and Simulation, pp. 103105, 1973.

Kuh, E.S., and L.K. Cheung, "Optimum Tearing of Large Systems and Minimum
Feedback Sets of a Digraph," Proceedings 5th Colloquium on Microwave
Communication, vol. II, Akademiai Kiado, Budapest, pp. 142152, 1974.

Cheung, L.K., and E.S. Kuh, "The Bordered Triangular Matrix and Minimum
Essential Sets of a Digraph," IEEE Trans. on Circuits and Systems,
vol. CAS21, no. 5, pp. 633639, September 1974.

Kuh, E.S., and B.S. Ting, "The Backboard Wiring Problem: Some Results on
SingleRow Routing," Proceedings IEEE Internatl. Symposium on Circuits
and Systems, pp. 369372, 1975.

Fujisawa, T., and E.S. Kuh, "Some Results on Existence and Uniqueness of
Solutions of Nonlinear Networks," Theory of Nonlinear Networks,
ed. by Alan N. Willson, IEEE Press, New York, pp. 389394, 1975.

Chien, M.J., and E.S. Kuh, "Solving PiecewiseLinear Equations for Resistive
Networks," International Journal of Circuit Theory and Applications,
vol. 4, no. 1, pp. 324, January 1976.

Ting, B.S., E.S. Kuh, and I. Shirakawa, "The Multilayer Routing Problem:
Algorithms and Necessary and Sufficient Conditions for the SingleRow,
SingleLayer Case," IEEE Trans. on Circuits and Systems, vol. CAS23,
no. 12, pp. 768778, December 1976.

Chien, M.J., and E.S. Kuh, "Solving Nonlinear Resistive Networks Using
PiecewiseLinear Analysis and Simplicial Subdivision," IEEE Trans. on
Circuits and Systems, vol. CAS24, no. 6, pp. 305317, June 1977.

Kuh, E.S., "Theory and Analysis of PiecewiseLinear Resistive Networks,"
Proceedings
of the Seventh International Conference on Nonlinear Circuits, vol.
2, no. 2, AkademieVerlag, Berlin, 1977.

Goto, S., and E.S. Kuh, "An Approach to the TwoDimensional Placement Problem
in Circuit Layout," IEEE Trans. on Circuits and Systems, vol. CAS25,
no. 4, pp. 208214, April 1978.

Ting, B.S., and E.S. Kuh, "An Approach to the Routing of Multilayer Printed
Circuit Boards," (with B.S. Ting), Proceedings IEEE Internatl. Symposium
on Circuits and Systems, pp. 902911, 1978.

Ting, B.S., E.S. Kuh, and A. SangiovanniVincentelli, "A Via Assignment
Problem in Multilayer Printed Circuit Board," IEEE Trans. on Circuits
and Systems, vol. CAS26, no. 4, pp. 261272, April 1979.

Tsukiyama, S., E.S. Kuh, and I. Shirakawa, "An Algorithm for SingleRow
SingleLayer Routing with Upper and Lower Street Congestions up to Two,"
The
Transactions of the Institute of Electronics and Communication Engineers
of Japan, vol. J62A, no. 5, pp. 309316, May 1979.

Kuh, E.S., T. Kashiwabara and T. Fujisawa, "On Optimum SingleRow Routing,"
IEEE
Trans. on Circuits and Systems, vol. CAS26, no. 6, pp. 361386, July
1979.

Ohtsuki, T., H. Mori, E.S. Kuh, T. Kashiwabara, and T. Fujisawa), "One
Dimensional Logic Gate Assignment and Interval Graphs," IEEE Trans.
on Circuits and Systems, vol. CAS26, no. 9, pp. 675684, September
1979.
1980  1989

Tsukiyama, S., E.S. Kuh, and I. Shirakawa, "An Algorithm for SingleRow
Routing with Prescribed Street Congestions," IEEE Trans. on Circuits
and Systems, vol. CAS27, no. 9, pp. 765772, September 1980.

Tsukiyama, S., E.S. Kuh, and Isao Shirakawa, "On the Layering Problem of
Multilayer PWB Wiring" 18th Design Automation Conference, pp. 738745,
July 1981. [NSF]

MarekSadowska, M., and E.S. Kuh, "A New Approach to Routing of TwoLayer
Printed Circuit Board," International Jour. of Circuit Theory and Applications,
vol. 9, no. 3, pp. 331341, July 1981. [NSF, JSEP, AFOSR, Humboldt]

Kuh, E.S., "Structured Routing in Circuit Layout  A Survey and Some New
Results," Circuit Theory and Design, (ed. R. Boite and P. DeWilde),
pp. 9596, 1981.

Yoshimura, T., and E.S. Kuh, "Efficient Algorithms for Channel Routing,"
IEEE
Trans. on ComputerAided Design of Integrated Circuits and Systems,
vol. CAD1, no. 1, pp. 2535, January 1982. [NSF, Humboldt]

MarekSadowska, M., and E.S. Kuh, "A New Approach to Channel Routing,"
Proc.
IEEE Int. Symp. on Circuits and Systems, pp. 764767, 1982. [NSF, AFOSR]

Tsukiyama, S., and E.S. Kuh, "DoubleRow Planar Routing and Permutation
Layout," Networks, pp. 287316, 1982.

Aoshima, K., and E.S. Kuh, "MultiChannel Optimization in GateArray LSI
Layout," Proc. IEEE Int. Symp. on Circuits and Systems pp. 10051089,
1983. [NSF]

Tsukiyama, S., E.S. Kuh, and I. Shirakawa "On the Layering Problem of Multilayer
PWB Wiring," IEEE Trans. on ComputerAided Design of Integrated Circuits
and Systems, vol. CAD2, no. 1, pp. 3038, January, 1983. [NSF]

MarekSadowska, M., and E.S. Kuh, "General ChannelRouting Algorithm,"
IEEE
Proc., Electronic Circuits and Systems vol. 130, pt. G, no. 3, pp.
8388, June 1983. [NSF, AFSC]

Chen, N.P., C.P. Hsu, and E.S. Kuh, "The Berkeley BuildingBlock Layout
System for VLSI Design," Proc. VLSI 83, (Eds. F. Anceau and E.J.
Aas) North Holland, pp. 3744, August, 1983. [NSF, AFSC]

Chen, N.P., C.P. Hsu, E.S. Kuh, C.C. Chen and M. Takahashi, "BBL: A Building
Block Layout System for Custom Chip Design," Proc. IEEE Int. Conf. on
ComputerAided Design, pp. 4041, September, 1983. [NSF, JSEP]

Cheng, C.K., and E.S. Kuh, "Partitioning and Placement Based on Network
Optimization," Proc. IEEE Int. Conf. on ComputerAided Design pp.
8687, September, 1983. [NSF, Hughes]

Kuh, E.S., "The StateVariable Approach to Network Analysis," Current
Contents, This Week's Citation Classic, vol. 14, no. 41, pp. 20, Oct.
1983.

Kuh, E.S., "Routing in Microelectronics  Editorial," IEEE Trans. on
ComputerAided Design of Integrated Circuits and Systems, vol. CAD2,
no. 4, pp. 213214, Oct. 1983.

Kuh, E.S., Editorial, Centennial Issue, IEEE Trans. on Circuits and
Systems, vol. CAS31, no. 1, pp. 2, January, 1984.

Li, J.T., C.K. Cheng, M. Turner, E.S. Kuh, and M. MarekSadowska, "Automatic
Layout of Gate Arrays," Proc. IEEE Custom Integrated Circuits Conf.,
pp. 518521, 1984. [SRC, Bell, Hughes]

Tarng, T.T., M. MarekSadowska, and E.S. Kuh, "An Efficient SingleRow
Routing Algorithm," IEEE Transactions on ComputerAided Design,
vol. CAD3, no. 3, pp. 178183, July 1984. [NSF, MICRO]

Cheng, C.K., and E.S. Kuh, "Module Placement Based on Resistive Network
Optimization," IEEE Transactions on ComputerAided Design, vol.
CAD3, no. 3, pp. 218225, July 1984. [NSF, Hughes]

Chen, C.C., and E.S. Kuh, "Automatic Placement for Building Block Layout,"
Proc.
Int. Conf. on ComputerAided Design, pp. 9092, November 1984. [NSF,
JSEP, AFOSR]

Fujita, T., and E.S. Kuh, "A New Detailed Routing Algorithm for Convex
Rectilinear Space," Proc. IEEE Int'l Conf. on ComputerAided Design,
p. 82, November 1984. [NSF, Bell]

Kuh, E.S., "Comments on the Evolution of Information Technologies," Information
Technologies and Social Transformation, National Academy of Engineering,
pp. 3334, 1985.

Dai, WM., T. Asano, and E.S. Kuh, "Routing Region Definition and Ordering
Scheme for BuildingBlock Layout," IEEE Trans. on ComputerAided Design,
vol. CAD4, no. 3, pp. 189197, July 1985. [AT&T, SRC, NSF]

Hu, T.C., and E.S. Kuh, eds., VLSI: Circuit Layout Theory and Techniques,
IEEE Press, October 1985.

Hu, T.C., and E.S. Kuh, "Theory and Concepts of Circuit Layout," in VLSI:
Circuit Layout Theory and Techniques, pp. 318, October 1985.

Chen, H., and E.S. Kuh, "A VariableWidth Gridless Channel Router," Proc.
Int. Conf. on ComputerAided Design, pp. 304306, November 1985. [SRC]

Kuh, E.S., and M. MarekSadowska, "Global Routing," Layout Design and
Verification, ed. T. Ohtsuki, North Holland, pp. 169198, 1986. [NSF,
SRC, MICRO]

Tsay, RS., and E.S. Kuh, "A Unified Approach to Circuit Partitioning and
Placement," Proc. Princeton Conference on Information Sciences &
Systems, pp. 155160, March 1986. [NSF, MICRO]

Kuh, E.S., "BuildingBlock Layout for Custom Integrated Circuit Design,"
Proc.
Eighth Colloquium on Microwave Communication, pp. 6971, August 1986.
[NSF]

Chen, H., and E.S. Kuh, "Glitter: A Gridless VariableWidth Channel Router,"
IEEE
Transactions on ComputerAided Design, vol. CAD5, no. 4, pp. 459465,
October 1986. [SRC, NSF]

Dai, WM., and E.S. Kuh, "Hierarchical Floor Planning for Building Block
Layout," Digest of Technical Papers, IEEE International Conference on
ComputerAided Design, pp. 454457, November 1986. [SRC]

Xiong, XM., and E.S. Kuh, "The Scan Line Approach to Power and Ground
Routing," Digest of Technical Papers, IEEE International Conference
on ComputerAided Design, pp. 69, November 1986.

Dai, WM., M. Sato, and E.S. Kuh, "Partial 3Trees and Applications to
Circuit Layout," Proceedings of IEEE International Symposium on Circuits
& Systems, pp. 3134, May 1987. [SRC, NSF]

Jackson, M.A.B., E.S. Kuh, and M. MarekSadowska, "TimingDriven Routing
for Building Block Layout," Proceedings of IEEE International Symposium
on Circuits & Systems, pp. 518519, May 1987. [NSF, JSEP]

Xiong, XM., and E.S. Kuh, "Nutcracker: An Efficient and Intelligent Channel
Spacer," Proceedings of 24th ACM/IEEE Design Automation Conference,
pp. 298304, June 1987. [SRC]

Dai, WM., M. Sato, and E.S. Kuh, "A Dynamic and Efficient Representation
of BuildingBlock Layout," Proceedings of 24th ACM/IEEE Design Automation
Conference, pp. 376384, June 1987. [SRC, NSF]

Dai, WM., and E.S. Kuh, "Global Spacing of Building Block Layout," Proceedings
of VLSI 1987, pp. 161174, August 1987. [SRC, NSF]

Dai, WM., and E.S. Kuh, "Simultaneous Floor Planning and Global Routing
for Hierarchical BuildingBlock Layout," IEEE Trans. on ComputerAided
Design, vol. CAD6, no. 5, pp. 828837, September 1987. [SRC, NSF]

Dai, WM., H. Chen, R. Dutta, M. Jackson, E.S. Kuh, M. MarekSadowska,
M. Sato, D. Wang, and XM. Xiong, "BEAR: A New BuildingBlock Layout System,"
Digest
of Technical Papers, IEEE International Conference on ComputerAided Design,
pp. 3437, November 1987. [SRC, NSF, JSEP, MICRO]

Tsay, RS., E.S. Kuh, and CP. Hsu, "PROUD: A Fast SeaofGates Placement
Algorithm," UCB/ERL Memorandum M87/79, November 1987.

Xiong, XM. and E.S. Kuh, "A Unified Approach to the Via Minization Problem,"
UCB/ERL Memorandum M87/80, November 1987.

Xu, DM., Y.K. Chen, E.S. Kuh, and Z.J. Li, "A New Algorithm with Gate
Matrix Layout," Proc. IEEE Int. Symp. on Circuits and Systems, pp.
288291, 1987.

Kuh, E.S., "Opportunities and Challenges in Research and Education for
Electrical Engineers," Science and Technology Review, vol. 1, no.
16, pp. 3841, 1988.

Xiong, XM., and E.S. Kuh, "The Constrained Via Minimization Problem for
PCB and VLSI Designs," Proceedings of 25th Design Automation Conference,
pp. 573578, June 1988. [SRC]

Tsay, RS., E.S. Kuh, and CP. Hsu, "PROUD: A Fast SeaofGates Placement
Algorithm," Proceedings of 25th Design Automation Conference, pp.
318323, June 1988. [NSF, JSEP, Hughes]

Cheng, KT., V.D. Agrawal, and E.S. Kuh, "A Sequential Circuit Test Generator
Using ThresholdValue Simulation," Proceedings of 18th Fault Tolerant
Computing Symposium, pp. 2429, June 1988. [NSF, MICRO]

Dai, WM., and E.S. Kuh, "BEAR: A New Macrocell Layout System for Custom
Chip Design," Extended Abstract Volume, SRC Techcon, pp. 4548,
October 1988. [SRC]

Tsay, RS., E.S. Kuh, and CP. Hsu, "Module Placement for Large Chips Based
on Sparse Linear Equations," International Journal of Circuit Theory
and Applications, vol. 16, pp. 411423, October 1988. [NSF, JSEP, Hughes]

Eschermann, B., WM. Dai, E.S. Kuh, and M. Pedram, "Hierarchical Placement
for Macrocells: A `Meet in the Middle' Approach," Digest of Technical
Papers, International Conference on ComputerAided Design, pp. 460463,
November 1988. [SRC, NSF]

Tsay, RS., E.S. Kuh, and CP. Hsu, "PROUD: A SeaOfGates Placement Algorithm,"
IEEE
Design and Test of Computers, pp. 4456, December 1988. [NSF, JSEP,
Hughes]

Xiong, XM., and E.S. Kuh, "A Unified Approach to the Via Minimization
Problem," IEEE Transactions on Circuits and Systems, vol. 36, no.
2, pp. 190204, February 1989. [SRC]

Spencer, W.J., J.Y. Chen, A. Chiang, W. Frieman, E.S. Kuh, J.L. Moll, R.F.
Pease, and K.C. Saraswat, "Chinese Microelectronics," Foreign Applied Sciences
Assessment Center Technical Assessment Report, Science Applications International
Corporation, April 1989.

Xiong, XM., and E.S. Kuh, "Geometric Compaction of BuildingBlock Layout,"
Proceedings
of IEEE Custom Integrated Circuits Conference, pp. 7.6.14, May 1989.
[SRC]

Jackson, M., and E.S. Kuh, "PerformanceDriven Placement of CellBaced
ICs," Proceedings of 26th Design Automation Conference, pp. 370375,
June 1989. [SRC]

Dai, W. WM., B. Eschermann, E.S. Kuh, and M. Pedram, "Hierarchial Placement
and Floorplanning in BEAR" IEEE Trans. on ComputerAided Design,
pp. 13351349, vol. 8, no. 12, December 1989. [SRC, NSF]
1990  1999

Kuh, E.S., and T. Ohtsuki, "Recent Advances in VLSI Layout," IEEE Proceedings
Special Issue on ComputerAided Design, vol. 78, no. 2, pp. 237263,
February 1990. [SRC, NSF, JSEP, JSEP]

Tsay, RS., and E.S. Kuh, "A Unified Approach to Partitioning and Placement,"
IBM Research Report RC15482 (#68859), February 9, 1990. [NSF, MICRO]

Srinivasan, A., and E.S. Kuh, "MOLE  A SeaofGates Detailed Router,"
Proceedings
of European Design Automation Conference, pp. 446450, March 1990 [JSEP,
NSF]

Jackson, M.A.B., A. Srinivasan, and E.S. Kuh, "A Novel Approach to IC Performance
Optimization by Clock Routing," UCB/ERL Memorandum M90/27, April 1990.

Jackson, M.A.B., and E.S. Kuh, "Estimating and Optimizing RC Interconnect
Delay During Physical Design," Proceedings of International Symposium
on Circuits and Systems, pp. 869871, May 1990. [NSF, SRC]

Xu, DM., E.S. Kuh, and YK. Chen, "An Extended 1D Assignment Problem:
Net Assignment in Gate Matrix Layout," Proceedings of International
Symposium on Circuits and Systems, pp. 16921696, May 1990. [NSF]

Ogawa, Y., M. Pedram, and E.S. Kuh, "TimingDriven Placement for General
Cell Layout," Proceedings of International Symposium on Circuits and
Systems, pp. 872876, May 1990. [NSF, SRC]

Jackson, M.A.B., A. Srinivasan, and E.S. Kuh, "Clock Routing for HighPerformance
ICs,"
Proceedings of 27th Design Automation Conference, pp. 573579,
June 1990. [SRC, JSEP, NSF]

Lin, S., M. MarekSadowska, and E.S. Kuh, "Delay and Area Optimization
in StandardCell Design," Proceedings of 27th Design Automation Conference,
pp. 349352, June 1990. [MICRO, NSF]

Xiong, XiaoMing and E.S. Kuh, "Geometric Approach to VLSI Layout Compaction,"
International
Journal on Circuit Theory and Applications, pp. 411430, July/August
1990. [SRC]

Kuh, E.S., A. Srinivasan, Michael A.B. Jackson, M. Pedram, Yasushi Ogawa,
and M. MarekSadowska, "TimingDriven Layout," Proc. Synthesis and Simulation
Meeting and International Interchange, pp. 263270, October 1990. [SRC,
NSF]

Pedram, M., M. MarekSadowska, and E.S. Kuh, "Floorplanning with Pin Assignment,"
Digest
of Technical Papers, Int. Conf. on ComputerAided Design, pp. 98101,
November 1990. [NSF, SRC, MICRO]

Jackson, M., A. Srinivasan, and E.S. Kuh, "A Fast Algorithm for PerformanceDriven
Placement," Digest of Technical Papers, Int. Conf. on ComputerAided
Design, pp. 328331, November 1990. [NSF, SRC, JSEP]

Wang, D., and E.S. Kuh, "Novel Routing Schemes for IC Layout Part I: TwoLayer
Channel Routing," UCB/ERL Memorandum M90/101, November 1990.

Wang, D., and E.S. Kuh, "Novel Routing Schemes for IC Layout Part II: ThreeLayer
Channel Routing," UCB/ERL Memorandum M90/102, November 1990.

Cheng, KwangTing, Vishwani D. Agrawal, and E.S. Kuh, "A SimulationBased
Method for Generating Tests for Sequential Circuits," IEEE Trans. on
Computers, Vol. 39, No. 12, pp. 14561463, December 1990. [NSF, MICRO]

Lin, S., M. MarekSadowska, and E.S. Kuh, "SWEC: A StepWise Equivalent
Conductance Timing Simulator for CMOS VLSI Circuits," pp. 142148, Proc.
European Design Automation Conference, February 1991. [NSF, MICRO]

Pedram, M., N. Bhat, K. Chaudhary, and E.S. Kuh, "Layout Considerations
in Combinational Logic Synthesis," Proc. International Workshop on Logic
Synthesis," May 1991. [NSF, SRC]

Srinivasan, A., K. Chaudhary, and E.S. Kuh, "RITUAL: PerformanceDriven
Placement of CellBased ICs," Proc. 3rd Physical Design Workshop,
May 1991. [NSF, SRC]

Tsay, RS. and Ernest Kuh, "A Unified Approach to Partitioning and Placement,"
IEEE
Trans. on Circuits and Systems, Vol. CAS38, No. 5, pp. 521533, May
1991.

Xu, DM., E.S. Kuh, and YK. Chen, "An Array Optimization Algorithm for
VLSI Layout," Proc. International Conf. on Circuits and Systems,
Shenzhen, China, June 1991.

Lin, S., and E.S. Kuh, "A New Approach to Circuit Simulation," Proc.
European Conf. on Circuit Theory and Design, pp. 264273, September
1991. [NSF, MICRO]

Shih, M., E.S. Kuh, and RS. Tsay, "PerformanceDriven System Partitioning
on MultiChip Modules," IBM Research Division Research Report RC 17315
(#76556), October 1991.

Wang, D., and E.S. Kuh, "New Algorithms for 2Layer and 3Layer Channel
Routing," Int. Journal of Circuit Theory and Applications, Vol. 19, No.
6, pp. 525549, November/December 1991.

Pedram, M., K. Chaudhary, and E.S. Kuh, "I/O Pad Assignment Based on the
Circuit Structure," Proc. ICCD, October 1991.

Srinivasan, A., K. Chaudhary, and E.S. Kuh, "RITUAL: A Performance Driven
Placement Algorithm for Small Cell ICs," Proc. Int. Conf. on ComputerAided
Design, pp. 4851, November 1991.

Srinivasan, A., K. Chaudhary, and E.S. Kuh, "RITUAL: A Performance Driven
Placement Algorithm," UCB/ERL Memorandum M91/103, November 1991.

Lin, S., E.S. Kuh, and M. MarekSadowska, "A New Accurate and Efficient
Timing Simulator," Proc. VLSI Design Conference, January 1992.

Lin, S., and E.S. Kuh, "Pade Approximation Applied to Transient Simulation
of Lossy Coupled Transmission Lines," Proc. IEEE MultiChip Module Conference,
pp. 5255, March 1992. [SRC]

Pedram, M., and E.S. Kuh, "BEARFP: A Robust Framework for Floorplanning,"
Int.
Journal of High Speed Electronics, Vol. 3, No. 1, pp. 137170, March
1992. [NSF, SRC]

Shih, M., E.S. Kuh, and RS. Tsay, "System Partitioning for MultiChip
Modules Under Timing and Capacity Constraints," Proc. IEEE MultiChip
Module Conference, pp. 123126, March 1992. [NSF, SRC]

Lin, S., and E.S. Kuh, "Pade Approximation Applied to Lossy Transmission
Line Circuit Simulation," Proc. Int. Symposium on Circuits and Systems,
pp. 9396, May 1992.

Hong, XL., J. Huang, CK. Cheng, and E.S. Kuh, "FARM: An Efficient FeedThrough
Pin Assignment Algorithm," Proc. Design Automation Conference, pp.
530535, June 1992. [NSF]

Lin, S., and E.S. Kuh, "Transient Simulation of Lossy Interconnect," Proc.
Design Automation Conference, pp. 8186, June 1992. [SRC]

Mitsuhashi, T., and E.S. Kuh, "Power and Ground Network Topology Optimization
for CellBased VLSIs," Proc. Design Automation Conference, pp. 524529,
June 1992

Shih, M., E.S. Kuh, and RS. Tsay, "PerformanceDriven Partitioning on
MultiChip Modules," Proc. Design Automation Conference, pp. 5356,
June 1992. [NSF, SRC]

Lin, S. and E.S. Kuh, "Transient Simulation of Lossy Coupled Transmission
Lines," Proc. European Design Automation Conference, pp. 126131,
September 1992. [SRC]

Lin, S., and E.S. Kuh, "Transient Simulation of Lossy Interconnects Based
on the Recursive Convolution Formulation," IEEE Trans. on Circuits and
Systems  I: Fund. Theory and Applications, Vol. 39, No. 11,
pp. 879892, November 1992. [SRC]

Srinivasan, A., Chaudhary, K., and E.S. Kuh, "RITUAL: A PerformanceDriven
Placement Algorithm," IEEE Trans. on Circuits and SystemsII: Analog
and Digital Signal Processing, Vol. 39, No. 11, pp. 825840, November
1992. [SRC, NSF]

Kuh, E.S. and M. Shih, "Recent Advances in TimingDriven Physical Design,"
Proc.
IEEE AsiaPacific Conference on Circuits and Systems, pp. 2328, December
1992.

Shih, M., E.S. Kuh, and RS. Tsay, "Integer Programming Techniques for
Multiway System Partitioning Under Timing and Capacity Constraints," Proc.
EDACEuroasic Conf., February 1993.

Shih, M., E.S. Kuh, and RS. Tsay, "TimingDriven System Partitioning by
Constraints Decoupling Method," Proc. 1993 IEEE Multichip Module Conf.,
pp. 164169, March 1993. [SRC]

Shih, M., and E.S. Kuh, "Quadratic Boolean Programming For PerformanceDriven
System Partitioning," UCB/ERL Memorandum M93/19, March 1993.

Lin, S. , E.S. Kuh, and M. MarekSadowska, "Stepwise Equivalent Conductance
Circuit Simulation Technique," IEEE Trans. on ComputerAided Design
of Integrated Circuits and Systems," Vol. 12, No. 5, pp. 672683, May
1993.

Hong, X., T. Xue, J. Huang, E.S. Kuh, and CK. Cheng, "Performancedriven
Steiner Tree Algorithms for Global Routing," Proc. 30th Design Automation
Conf., pp. 177181, June 1993.

Huang, J., X. Hong, CK. Cheng, and E.S. Kuh, "An Efficient TimingDriven
Global Routing Algorithm," Proc. 30th Design Automation Conf., pp.
596600, June 1993.

Shih, M., and E.S. Kuh, "Quadratic Boolean Programming for PerformanceDriven
System Partitioning," Proc. 30th Design Automation Conf., pp. 761765,
June 1993.

Bhat, N., K. Chaudhary, and E.S. Kuh, "PerformanceOriented Fully Routable
Dynamic Architecture for a FieldProgrammable Logic Device," UCB/ERL Memorandum
M93/42, June 1993.

Lin, S., and E.S. Kuh, "Fast and Accurate Simulation of Large Lossy Interconnect
Networks Using Circuit Partition and Recursive Convolution," Proc. European
Conf. on Circuit Theory and Design, pp. 15491553, August 1993.

Shih, M. and E.S. Kuh, "TimingDriven System Partitioning by Generalized
Burkard's Heuristic," Proc. European Conf. on Circuit Theory and Design,
pp. 15431548, August 1993. [SRC]

Lin, S. and E.S. Kuh, "Circuit Simulation for Large Interconnected IC Networks,"
Proc.
VLSI 93, pp. 9.1.110, September 1993.

Xue, T., T. Fujii, and E.S. Kuh, "A New PerformanceDriven Global Routing
Algorithm for Gate Array," Proc. VLSI 93, pp. 8.3.110, September
1993.

Shih, M., and E.S. Kuh, "TechnologyDriven Circuit Partitioning," Extended
Abstract Volume, SRC Techcon '93, pp. 207209, September 1993.

Chaudhary, K., A. Onozawa, and E.S. Kuh, "A Spacing Algorithm for Performance
Enhancement and Crosstalk Reduction," Digest of Technical Papers,
IEEE/ACM Int. Conf. on CAD, pp. 697702, November 1993.

Shih, M., and E.S. Kuh, "Quadratic Boolean Programming for PerformanceDriven
System Partitioning," UCB/ERL Memorandum M9319, March 1993 (Revised 23
November 1993).

Yu, Q., and E.S. Kuh, "Moment Models of General Transmission Lines with
Application to Interconnect Analysis," Proceedings of the IEEE MultiChip
Module Conference MCMC 95, pp. 152157, January, 1995.

Lin, Shen and Ernest S. Kuh, "SWEC Speeds VLSI Simulations," IEEE Circuits
and Devices, Vol. 11, No. 1, pp. 1015, January 1995.

* Buch, P., Lin, S., Nagasamy, V., and E.S. Kuh, "Techniques for Fast Circuit
Simulation Applied to Power Estimation of CMOS Circuits," Proceedings of
the 1995 International Symposium on Low Power Design, pp. 135138,
April 1995.

* Hough, C., Xue, T., and E.S. Kuh, "New Approaches for OnChip Power Switching
Noise Reduction," Proceedings of the IEEE 1995 Custom Integrated Circuits
Conference, pp. 133136, May, 1995.

Onozawa, A., Chaudhary, K., and E.S. Kuh, "Performance Driven Spacing Algorithms
Using Attractive and Repulsive Constraints for Submicron LSI's," IEEE
Transactions on ComputerAided Design of Integrated Circuits and Systems,
Vol. 14, No. 6, pp. 707719, June 1995.

Yu, Q., and E.S. Kuh, "Moment Matching Model of Transmission Lines and
Application to Interconnect Delay Estimation," IEEE Transactions on
VLSI Systems, Vol. 3, No. 2, pp. 311322, June, 1995.

Dongmin, X., Chen, Y.K., and E.S. Kuh, "An Array Optimization Algorithm
for VLSI Layout," Journal of Tsinghua University (Sci & Tech),
Vol. 35, No. 1, pp. 19, 1995.

Xue, T., and E.S. Kuh, "Post Routing Performance Optimization via MultiLink
Insertion and NonUniform Wiresizing," Proceedings of the ICCAD '95,
San Jose, CA, November 59, 1995, pp. 575580.

Wang, D.S., and E.S. Kuh, "PerformanceDriven Interconnect Global Routing,"
Proceedings of the 1996 Great Lakes Symposium on VLSI, pp. 132136,
March, 1996.

Yu, Q. and Ernest S. Kuh, "An Accurate Time Domain Interconnect Model of
Transmission Line Networks," IEEE Transactions on Circuits and Systems,
Vol. 43, No. 3, pp. 200208, March 1996.

Xue, T, Yu, Q., and E.S. Kuh, "A SensitivityBased Wiresizing Approach
to Interconnect Optimization of Lossy Transmission Line Topologies," Proceedings
of the 1996 IEEE MultiChip Module Conference, pp. 117121, February,
1996.

Esbensen, H., and E.S. Kuh, "An MCM/IC TimingDriven Placement Algorithm
Featuring Explicit Design Space Exploration," Proceedings of the 1996
IEEE MultiChip Module Conference, pp. 170175, February, 1996.

Esbensen, H., and E.S. Kuh, "Design Space Exploration Using the Genetic
Algorithm," Proceedings of the 1996 IEEE International Symposium on
Circuits and Systems, pp. 500503, May, 1996.

Esbensen, H., and E.S. Kuh, "Explorer: An Interactive Floorplanner for
Design Space Exploration," Proc. EuroDAC'96, pp. 356361, September
1996.

Xue, T., E.S. Kuh, and D.S. Wang, "Post Global Routing Crosstalk Risk Estimation
and Reduction," Proceedings of the IEEE/ACM Int'l Conf. on ComputerAided
Design, pp. 302309, November, 1996.

Mao, JM., J.M. Wang, and E.S. Kuh, "Simulation and Sensitivity Analysis
of Transmission Line Circuits by the Characteristics Method," ICCAD'96,
pp. 556562, November, 1996.

Yu, Q., E.S. Kuh and T. Xue, "Moment Models of General Transmission Line
with Application to Interconnect Analysis and Optimization," IEEE Trans.
on VLSI Systems, Vol. 4, No. 4, pp. 477494, December, 1996.

Buch, P., and E.S. Kuh, "Symphony: A Fast Mixed Signal Simulator for BiMOS
Analog/Digital Circuits," Proceedings of the 10th International Conference
on VLSI Design '97, pp. 403407, January, 1997.

Esbensen, H., and E.S. Kuh, "A PerformanceDriven IC/MCM Placement Algorithm
Featuring Explicit Design Space Exploration," ACM Transactions on Design
Automation of Electronic Systems, pp. 6280, January 1997.

Wang, D.S., E.S. Kuh, "A New TimingDriven Multilayer MCM/IC Routing Algorithm,"
Proc. MCMC'97, pp. 8994, February, 1997.

Mao, J.F., and E.S. Kuh, "Fast Simulation and Sensitivity Analysis of
Lossy Transmission Lines by the Method of Characteristics," IEEE Transactions
on Circuits and Systems, pp. 391401, May 1997.

Yu, Q., and E.S. Kuh, "Reduced order model of transmission lines with preservation
of passivity and moment matching at multiple points," 1997 Intl. Symp.
on Nonlinear Theory and its Applications (NOLTA'97), pp. 845848, Nov.
1997.

Hong, X., T. Xue, J. Huang, C.K. Cheng, and E.S. Kuh, "TIGER: An Efficient
Timing  Driven Global Router for Gate Array and Standard Cell LayoutDesign,"
IEEE
Trans. ComputerAided Design, Vol. 16, No. 11, pp. 13231331, Nov.
1997.

Wang, D.S., and E.S. Kuh, "PerformanceDriven MCM Router with Special Consideration
of Crosstalk Reduction," to appear in Proceeding of EuroDAC'98.

Kuh, E.S., "Emerging DSM Interconnect Tools, and interview with Prof. Ernest
S. Kuh," Integrated System DesignElectronics Journal, pp. 2325,
Dec. 1997.

Murata, H., E.S. Kuh, "SequencePair Based Placement Method for Hard/Soft/Preplaced
Modules," ISPD'98, pp. 167172.

Yu, Q., J.M. Wang, and E.S. Kuh, "Reduced order model of RLC interconnects
with multipoint moment matching and passivity preservation," ISCAS'98,
Vol. VI, pp. 7477, 1998.

Wang, D. and E.S. Kuh, "A New General Connectivity Model and Its Applications
to TimeingDriven Steiner Tree Routing," 1998 IEEE International Conference
on Electronic Circuits and Systems 7272, 1998.

Yu, Q., Wang, J., and E.S. Kuh, "Multipoint Moment Matching Model for Multiport
Distributed Interconnect, " IEEE/ACM International Conference on ComputerAided
Design, pp.8591, Nov. 1998.

Yu, Q., J.M. Wang, and E.S. Kuh, "Passive Multipoint Moment Model Order
Reduction Algorithm on Multiport Distributed Interconnect Networks, "
IEEE Trans. Ciruits and Systems, I, Vol.46, No. 1 pp. 140160, January,
1999.

J.M. Wang, Q. Yu, and E.S. Kuh, "Coupled Noise Estimation for Distributed
RC Interconnect Model," in Proceedings DATE 1999, pp. 664668.

J.M. Wang, E.S. Kuh and Qingjian Yu, "The Chebyshev expansion based
passive model for distributed interconnect networks,” Proceedings
ICCAD 99, pp 370375.
2000  Present

Pinhong Chen and Ernest S. Kuh, "Floorplan Sizing by Linear Programming
Approximation,” Proceedings 37th Design Automation Conference,
pp 468472, June 2000.

Qingjian Yu, J.M Wang and Ernest S. Kuh, "Passive Model Order Reduction
Algorithm based on Chebyshev Expansion of Impulsive Response of Interconnect
Networks,” Proceedings 37th Design Automation Conference,
pp 520525, June, 2000.

J. M. Wang, and E.S. Kuh, “Recent Development in Interconnect Modeling,”
Interconnects
in VLSI Design Kluwer Academic Publications pp. 123, 2000.

E.S. Kuh, “Circuit Theory and Interconnect Analysis for DSM Chip Design,”
Proceedings
IEEE Asia Pacific Conterence on Circuits and Systems, pp. 13, December,
2000.

E.S. Kuh and O.J. Yu, "Explicit formulas and Efficient Algorithm for Moment
Computation of Coupled RC Trees," Proc. DATE, pp. 445450, March 12, 2001.

E.S. Kuh, "Recent Advance on Circuit and Interconnect Simulation for Deep
Submicron IC Design," Proc. Signal Propagation in Interconnect, May 13,
2001.
 E.S. Kuh and Q.J. Yu, "Moment Computation of Lumped and Distributed
Coupled RC Trees with Application to Delay and Crosstalk Estimation,"
Proc. IEEE, Vol. 89, No.5, pp. 772788, May, 2001.
 E.S. Kuh and Q.J. Yu, "New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees," Proc. Quality Electronic Design, pp. 151157, 2001.
 E.S. Kuh and Q.J. Yu, "Passive TimeDomain Model Order Reduction
via Orthonormal Basis Fruitions," Proc. 15th European Conf. on
Circuit Theory and Design, Vol. III, pp. 3740, 2001.
 J.M. Wang, C. Chu, Q. Yu, and E. S. Kuh, "On ProjectionBased Algorithms for ModelOrder Reduction of Interconnects," IEEE Trans. Circuits and Systems, Part I, Vol. 49, No. 11, pp 15631585, Nov. 2002.
 E.S. Kuh and ChiPing Hsu, "Physical Design Overview," The Best of ICCAD, Kluwer Acad. Publishers, pp 467477, 2003.
 I.W. Sandberg and Ernest S. Kuh, "Sidney Darlington 19061997," National Academy of Sciences, Biographical Memoirs, Vol. 84.
 Z. Zhu, K. Rouz, M. Borah, C.K. Cheng, and E.S. Kuh, "Efficient Transient Simulation for TransistorLevel Analysis," ASPDAC, pp. 240243, 2005.
 H. Zhu, C. K. Cheng, Rouz, Borah, and Ernest S. Kuh, "TwoStage NewtonRaphson Method fro TransistorLevel Simulation," Trans. IEEE on ComputerAided Design of Integrated Circuits and Systems, Vol.26, No.5, May 2007, pp 881893.
 L. Zhang, W. Yu, H. Zhu, A. Deutsch, G. Katopis, D. Dreps, E.S. Kuh, and C.K. Cheng, "Low Power Passive Equalizer Optimization using Tritonic Step Response," IEEE/ACM Design Automation Conf. 2008.
 R. Shi, W. Yu, C.K. Cheng, E.S. Kuh, "Efficient and Accurate Eye Diagram Prediction for High Speed Signaling," ACM/IEEE Int. Conf. on ComputerAided Design, 2008.
