PUBLICATIONS

E.S. Kuh - Publications

Books

  1. Kuh, E.S. and D.O. Pederson, Principles of Circuit Synthesis, McGraw-Hill, New York, 1959, 244 pages.
  2. Kuh, E.S. and R.A. Rohrer, Theory of Linear Active Networks, Holden-Day, Inc., San Francisco, CA, 1967, 650 pages.
  3. Desoer, C.A., and E.S. Kuh, Basic Circuit Theory, McGraw-Hill, New York, 1969, 876 pages. Italian translation, 1972. Chinese translation, 1972. Russian translation, 1976. Japanese translation, 1977. Portuguese translation, 1979. PRC translation, 1979.
  4. Chua, L.O., C.A. Desoer, and E.S. Kuh, Linear and Nonlinear Circuits, McGraw Hill, New York, 1987, 839 pages.
  5. Kuh, E.S., editor, Multichip Modules, World Scientific, Singapore, 1992, 145 pages.
  6. Hu, T.C., and E.S. Kuh, eds., VLSI: Circuit Layout Theory and Techniques, IEEE Press, October 1985.

Papers

1950  - 1959 / 1960 - 1969 / 1970 - 1979 / 1980 - 1989 / 1990 - 1999 / 2000 - present
  1. Kuh, E.S., "Potential Analog Network Synthesis for Arbitrary Loss Functions," J. of Applied Physics, vol. 24, no. 7, pp. 897-902, July 1953.
  2. Kuh, E.S., "Parallel Ladder Realization of Transfer Admittance Functions," Proc. of the Natl. Electronics Conf., vol. 10, pp. 198-206, October 1954.
  3. Kuh, E.S., "Special Synthesis Techniques for Driving Point Impedance Functions," IRE Trans. on Circuit Theory, CT-2, no. 4, pp. 302-308, December 1955.
  4. Kuh, E.S., Review of "Elementary Operations which Generate Network Matrices," by R.J. Dufflin, Am. Math. Soc. Trans., June 1955; published in IRE Trans. on Circuit Theory, CT-3, no. 2, p. 152, June 1956.
  5. Kuh, E.S., "Synthesis of Lumped Parameter Decision Delay Line," Proc. of the IRE, vol. 45, no. 112, pp. 1632-1642, December 1957.
  6. Kuh, E.S., Review of Network Synthesis, by N. Balabanian, Prentice Hall, 1958; published in Proc. of the IRE, vol. 46, no. 2, p. 348, February 1958.
  7. Kuh, E.S., "Synthesis of RC Grounded Two-Ports," IRE Trans. on Circuit Theory, CT-5, no. 1, pp. 55-61, March 1958.

  8.  

     

    1960-1969
     

  9. Paige, A., and E.S. Kuh, "Maximum Gain Realization of an RC Ladder Network," IRE Trans. on Circuit Theory, CT-7, pp. 32-40, March 1960.
  10. Kuh, E.S., "Regenerative Modes of Active Networks," IRE Trans. on Circuit Theory, CT-7, pp. 62-63, March 1960.
  11. Desoer, C.A., and E.S. Kuh, "Bounds on Natural Frequencies of Linear Active Networks," Proc. of Active Networks and Feedback Systems, Polytechnic Institute of Brooklyn, pp. 415-436, April 1960.
  12. Kuh, E.S., Review of Laplace Transforms for Electronic Engineers, by J.G. Holbrook, Pergamon Press, 1959; published in Proc. of the IRE, vol. 48, no. 7, p. 1350, July 1960.
  13. Kuh, E.S., "Voltage Transfer Function Synthesis of Active RC Networks," IRE Trans. on Circuit Theory, CT-7, pp. 134-138, August 1960.
  14. Kuh, E.S., and J.D. Patterson, "Design Theory of Optimum Negative-Resistance Amplifiers," Proc. of the IRE, vol. 49, no. 6, pp. 1043-1050, June 1961.
  15. Kuh, E.S., and M. Fukada, "Optimum Synthesis of Wide-Band Parametric Amplifiers and Convertors," IRE Trans. on Circuit Theory, CT-8, pp. 410-415, December 1961.
  16. Kuh, E.S., "Theory and Design of Wide-Band Parametric Convertors," Proc. of the IRE, vol. 50, no. 1, pp. 31-38, January 1962.
  17. Kuh, E.S., Network Theory: "Generalized Equations and Topological Analysis," The Encyclopedia of Electronics, pp. 524-526, Reinhold Publishing Corp., 1962.
  18. Kuh, E.S., "Some Results in Linear Multiple Loop Feedback Systems," Proc. of the Allerton Conf. on Circuit and Systems Theory, vol. 1, pp. 471-483, November 1963.
  19. Kuh, E.S., "Time-Varying Networks -- the State Variable, Stability and Energy Bounds," The Inst. of Electronics and Communications Engineers of Japan, ICMCI Summary, Part II, pp. 91-92, 1964.
  20. Kuh, E.S., and R.A. Rohrer, "The State-Variable Approach to Network Analysis," Proc. of the IEEE, vol. 53, no. 7, pp. 672-686, July 1965.
  21. Kuh, E.S., "Stability of Linear Time-Varying Networks -- The State Space Approach," IEEE Trans. on Circuit Theory, CT-12, no. 2, pp. 150-157, June 1965.
  22. Kuh, E.S., Review of Circuits with Periodically Varying Parameters, by D.G. Tucker, Van Nostrand, 1965; published in Proc. of the IEEE, vol. 53, no. 8, pp. 1166-1167, August 1965.
  23. Biswas, R.N., and E.S. Kuh, "Multiparameter Sensitivity Analysis for Linear Systems," Proc. of the Allerton Conf. on Circuit and System Theory, vol. 3, pp. 384-393, October 1965.
  24. Kuh, E.S., "Representation of Nonlinear Networks," Proc. of the Natl. Electronics Conference, vol. 21, pp. 702-707, October 1965.
  25. Chan, T.Y., and E.S. Kuh, "A General Matching Theory and Its Application to Tunnel Diode Amplifiers," IEEE Trans. on Circuit Theory, CT-3, no. 1, pp. 6-18, March 1966.
  26. Kuh, E.S., "Nonlinear and Time-Variable Networks," Acta Polytechnica, Prace Cvut, V. Praze, vol. IV, no. 1, pp. 87-98, 1966.
  27. Kuh, E.S., D.M. Layton, and J. Tow, "Network Analysis and Synthesis Via State Variables," ERL/UCB Memorandum M169, July 1966.
  28. Kuh, E.S., D.M. Layton, and J. Tow, "Network Analysis and Synthesis via State Variables," in Network and Switching Theory, Academic Press, N.Y., 1968.
  29. Kuh, E.S., "A Minimum-Sensitivity Multiple-Loop Feedback Design," Proc. of the Hawaii Internatl. Conf. on System Science, pp. 53-56, 1968.
  30. Biswas, R.N., and E.S. Kuh, "Multiple Loop Feedback Synthesis and Sensitivity Optimization," Proc. of the Circuit Theory Conf., Prague, Czechoslovakia, pp. 1-15, July 1968.
  31. Kuh, E.S., and C.G. Lau, "Sensitivity Invariants of Continuously Equivalent Networks," IEEE Trans. on Circuit Theory, CT-15, no. 3, pp. 175-177, September 1968.
  32. Kuh, E.S., "State Variables and Feedback Theory," IEEE Trans. on Circuit Theory, CT-16, no. 1, pp. 23-26, February 1969.
  33. Kuh, E.S., "Progress in Radio Waves and Transmission of Information: Information Theory, Circuit Theory and Computer-Aided Design," Radio Science, vol. 4, no. 7, pp. 651-656, July 1969.

  34.  

     

    1970 - 1979
     

  35. Desoer, C.A., and E.S. Kuh, "Teaching Basic Circuit Theory for the 1970's," in ects of Network and System Theory, eds., R.E. Kalman and N. DeClaris, Holt, Rinehart and Winston, pp. 627-639, 1971.
  36. Kuh, E.S., and I.N. Hajj, "Nonlinear Circuit Theory: Resistive Networks," Proc. of the IEEE, vol. 59, no. 3, pp. 340-355, March 1971.
  37. Kuh, E.S., "Circuits, Feedback and Dynamical Systems," Japanese J. of Systems and Control, vol. 15, no. 3, pp. 204-211, 1971.
  38. Fujisawa, T., and E.S. Kuh, "Piecewise-Linear Theory of Nonlinear Resistive Networks," Internatl. Conf. on Systems, Networks and Computers, Oaxtepec, Mexico, pp. 112-113, January 1971.
  39. Fujisawa, T., and E.S. Kuh, "Some Results on Existence and Uniqueness of Solutions of Nonlinear Networks," IEEE Trans. on Circuit Theory, CT-18, no. 5, pp. 501-506, September 1971.
  40. Kuh, E.S., Dertouzos, Bashkow, Carlin, Rowe, Smullin and Van Valkenburg, "Insights vs. Algorithms: A Leader's View," IEEE Trans. on Education, E-14, no. 4, pp. 164-169, November 1971.
  41. Biswas, R.N., and E.S. Kuh, "Optimum Synthesis of a Class of Multiple-Loop Feedback Systems," IEEE Trans. on Circuit Theory, CT-18, no. 6, pp. 582-587, November 1971.
  42. Biswas, R.N., and E.S. Kuh, "A Multiparameter Sensitivity Measure for Linear Systems," IEEE Trans. on Circuit Theory, CT-18, no. 6, pp. 718-719, November 1971.
  43. Kuh, E.S., and H. Abed, "Invertability, Reproducibility and Decoupling of a Class of Nonlinear Systems," IEEE Decision and Control Conf., pp. 61-68, December 1971.
  44. Fujisawa, T., and E.S. Kuh, "Piecewise-Linear Theory of Nonlinear Networks," SIAM J. on Applied Mathematics, vol. no. 2, pp. 307-328, March 1972.
  45. Fujisawa, T., E.S. Kuh, and T. Ohtsuki, "A Sparse Matrix Method for Analysis of Piecewise-Linear Resistive Networks," IEEE Trans. on Circuit Theory, CT-19, no. 6, pp. 571-584, November 1972.
  46. Kuh, E.S., "Sparse Matrix Method for Analysis of Large Networks," in Network and Signal Theory, (J.K. Skwirzynski and J.O. Scanlon, Peter Peregrinus Ltd., London), pp. 119-121, 1972.
  47. Cheung, L.K., and E.S. Kuh, "A Graph-Theoretic Method for Optimal Partitioning of Large Sparse Matrices," Proc. 6th Hawaii Internatl. Conf. on System Sciences (second supplement), pp. 45-48, 1973.
  48. Kuh, E.S., "Partitioning and Tearing of Large Scale Systems," Proceedings 4th Pittsburgh. Conf. on Modeling and Simulation, pp. 103-105, 1973.
  49. Kuh, E.S., and L.K. Cheung, "Optimum Tearing of Large Systems and Minimum Feedback Sets of a Digraph," Proceedings 5th Colloquium on Microwave Communication, vol. II, Akademiai Kiado, Budapest, pp. 142-152, 1974.
  50. Cheung, L.K., and E.S. Kuh, "The Bordered Triangular Matrix and Minimum Essential Sets of a Digraph," IEEE Trans. on Circuits and Systems, vol. CAS-21, no. 5, pp. 633-639, September 1974.
  51. Kuh, E.S., and B.S. Ting, "The Backboard Wiring Problem: Some Results on Single-Row Routing," Proceedings IEEE Internatl. Symposium on Circuits and Systems, pp. 369-372, 1975.
  52. Fujisawa, T., and E.S. Kuh, "Some Results on Existence and Uniqueness of Solutions of Nonlinear Networks," Theory of Nonlinear Networks, ed. by Alan N. Willson, IEEE Press, New York, pp. 389-394, 1975.
  53. Chien, M.J., and E.S. Kuh, "Solving Piecewise-Linear Equations for Resistive Networks," International Journal of Circuit Theory and Applications, vol. 4, no. 1, pp. 3-24, January 1976.
  54. Ting, B.S., E.S. Kuh, and I. Shirakawa, "The Multilayer Routing Problem: Algorithms and Necessary and Sufficient Conditions for the Single-Row, Single-Layer Case," IEEE Trans. on Circuits and Systems, vol. CAS-23, no. 12, pp. 768-778, December 1976.
  55. Chien, M.J., and E.S. Kuh, "Solving Nonlinear Resistive Networks Using Piecewise-Linear Analysis and Simplicial Subdivision," IEEE Trans. on Circuits and Systems, vol. CAS-24, no. 6, pp. 305-317, June 1977.
  56. Kuh, E.S., "Theory and Analysis of Piecewise-Linear Resistive Networks," Proceedings of the Seventh International Conference on Nonlinear Circuits, vol. 2, no. 2, Akademie-Verlag, Berlin, 1977.
  57. Goto, S., and E.S. Kuh, "An Approach to the Two-Dimensional Placement Problem in Circuit Layout," IEEE Trans. on Circuits and Systems, vol. CAS-25, no. 4, pp. 208-214, April 1978.
  58. Ting, B.S., and E.S. Kuh, "An Approach to the Routing of Multilayer Printed Circuit Boards," (with B.S. Ting), Proceedings IEEE Internatl. Symposium on Circuits and Systems, pp. 902-911, 1978.
  59. Ting, B.S., E.S. Kuh, and A. Sangiovanni-Vincentelli, "A Via Assignment Problem in Multilayer Printed Circuit Board," IEEE Trans. on Circuits and Systems, vol. CAS-26, no. 4, pp. 261-272, April 1979.
  60. Tsukiyama, S., E.S. Kuh, and I. Shirakawa, "An Algorithm for Single-Row Single-Layer Routing with Upper and Lower Street Congestions up to Two," The Transactions of the Institute of Electronics and Communication Engineers of Japan, vol. J62A, no. 5, pp. 309-316, May 1979.
  61. Kuh, E.S., T. Kashiwabara and T. Fujisawa, "On Optimum Single-Row Routing," IEEE Trans. on Circuits and Systems, vol. CAS-26, no. 6, pp. 361-386, July 1979.
  62. Ohtsuki, T., H. Mori, E.S. Kuh, T. Kashiwabara, and T. Fujisawa), "One Dimensional Logic Gate Assignment and Interval Graphs," IEEE Trans. on Circuits and Systems, vol. CAS-26, no. 9, pp. 675-684, September 1979.

  63.  

     

    1980 - 1989
     

  64. Tsukiyama, S., E.S. Kuh, and I. Shirakawa, "An Algorithm for Single-Row Routing with Prescribed Street Congestions," IEEE Trans. on Circuits and Systems, vol. CAS-27, no. 9, pp. 765-772, September 1980.
  65. Tsukiyama, S., E.S. Kuh, and Isao Shirakawa, "On the Layering Problem of Multilayer PWB Wiring" 18th Design Automation Conference, pp. 738-745, July 1981. [NSF]
  66. Marek-Sadowska, M., and E.S. Kuh, "A New Approach to Routing of Two-Layer Printed Circuit Board," International Jour. of Circuit Theory and Applications, vol. 9, no. 3, pp. 331-341, July 1981. [NSF, JSEP, AFOSR, Humboldt]
  67. Kuh, E.S., "Structured Routing in Circuit Layout -- A Survey and Some New Results," Circuit Theory and Design, (ed. R. Boite and P. DeWilde), pp. 95-96, 1981.
  68. Yoshimura, T., and E.S. Kuh, "Efficient Algorithms for Channel Routing," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, no. 1, pp. 25-35, January 1982. [NSF, Humboldt]
  69. Marek-Sadowska, M., and E.S. Kuh, "A New Approach to Channel Routing," Proc. IEEE Int. Symp. on Circuits and Systems, pp. 764-767, 1982. [NSF, AFOSR]
  70. Tsukiyama, S., and E.S. Kuh, "Double-Row Planar Routing and Permutation Layout," Networks, pp. 287-316, 1982.
  71. Aoshima, K., and E.S. Kuh, "Multi-Channel Optimization in Gate-Array LSI Layout," Proc. IEEE Int. Symp. on Circuits and Systems pp. 1005-1089, 1983. [NSF]
  72. Tsukiyama, S., E.S. Kuh, and I. Shirakawa "On the Layering Problem of Multilayer PWB Wiring," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, no. 1, pp. 30-38, January, 1983. [NSF]
  73. Marek-Sadowska, M., and E.S. Kuh, "General Channel-Routing Algorithm," IEEE Proc., Electronic Circuits and Systems vol. 130, pt. G, no. 3, pp. 83-88, June 1983. [NSF, AFSC]
  74. Chen, N.P., C.P. Hsu, and E.S. Kuh, "The Berkeley Building-Block Layout System for VLSI Design," Proc. VLSI 83, (Eds. F. Anceau and E.J. Aas) North Holland, pp. 37-44, August, 1983. [NSF, AFSC]
  75. Chen, N.P., C.P. Hsu, E.S. Kuh, C.C. Chen and M. Takahashi, "BBL: A Building Block Layout System for Custom Chip Design," Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 40-41, September, 1983. [NSF, JSEP]
  76. Cheng, C.K., and E.S. Kuh, "Partitioning and Placement Based on Network Optimization," Proc. IEEE Int. Conf. on Computer-Aided Design pp. 86-87, September, 1983. [NSF, Hughes]
  77. Kuh, E.S., "The State-Variable Approach to Network Analysis," Current Contents, This Week's Citation Classic, vol. 14, no. 41, pp. 20, Oct. 1983.
  78. Kuh, E.S., "Routing in Microelectronics - Editorial," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, no. 4, pp. 213-214, Oct. 1983.
  79. Kuh, E.S., Editorial, Centennial Issue, IEEE Trans. on Circuits and Systems, vol. CAS-31, no. 1, pp. 2, January, 1984.
  80. Li, J.T., C.K. Cheng, M. Turner, E.S. Kuh, and M. Marek-Sadowska, "Automatic Layout of Gate Arrays," Proc. IEEE Custom Integrated Circuits Conf., pp. 518-521, 1984. [SRC, Bell, Hughes]
  81. Tarng, T.T., M. Marek-Sadowska, and E.S. Kuh, "An Efficient Single-Row Routing Algorithm," IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 3, pp. 178-183, July 1984. [NSF, MICRO]
  82. Cheng, C.K., and E.S. Kuh, "Module Placement Based on Resistive Network Optimization," IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 3, pp. 218-225, July 1984. [NSF, Hughes]
  83. Chen, C.C., and E.S. Kuh, "Automatic Placement for Building Block Layout," Proc. Int. Conf. on Computer-Aided Design, pp. 90-92, November 1984. [NSF, JSEP, AFOSR]
  84. Fujita, T., and E.S. Kuh, "A New Detailed Routing Algorithm for Convex Rectilinear Space," Proc. IEEE Int'l Conf. on Computer-Aided Design, p. 82, November 1984. [NSF, Bell]
  85. Kuh, E.S., "Comments on the Evolution of Information Technologies," Information Technologies and Social Transformation, National Academy of Engineering, pp. 33-34, 1985.
  86. Dai, W-M., T. Asano, and E.S. Kuh, "Routing Region Definition and Ordering Scheme for Building-Block Layout," IEEE Trans. on Computer-Aided Design, vol. CAD-4, no. 3, pp. 189-197, July 1985. [AT&T, SRC, NSF]
  87. Hu, T.C., and E.S. Kuh, eds., VLSI: Circuit Layout Theory and Techniques, IEEE Press, October 1985.
  88. Hu, T.C., and E.S. Kuh, "Theory and Concepts of Circuit Layout," in VLSI: Circuit Layout Theory and Techniques, pp. 3-18, October 1985.
  89. Chen, H., and E.S. Kuh, "A Variable-Width Gridless Channel Router," Proc. Int. Conf. on Computer-Aided Design, pp. 304-306, November 1985. [SRC]
  90. Kuh, E.S., and M. Marek-Sadowska, "Global Routing," Layout Design and Verification, ed. T. Ohtsuki, North Holland, pp. 169-198, 1986. [NSF, SRC, MICRO]
  91. Tsay, R-S., and E.S. Kuh, "A Unified Approach to Circuit Partitioning and Placement," Proc. Princeton Conference on Information Sciences & Systems, pp. 155-160, March 1986. [NSF, MICRO]
  92. Kuh, E.S., "Building-Block Layout for Custom Integrated Circuit Design," Proc. Eighth Colloquium on Microwave Communication, pp. 69-71, August 1986. [NSF]
  93. Chen, H., and E.S. Kuh, "Glitter: A Gridless Variable-Width Channel Router," IEEE Transactions on Computer-Aided Design, vol. CAD-5, no. 4, pp. 459-465, October 1986. [SRC, NSF]
  94. Dai, W-M., and E.S. Kuh, "Hierarchical Floor Planning for Building Block Layout," Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pp. 454-457, November 1986. [SRC]
  95. Xiong, X-M., and E.S. Kuh, "The Scan Line Approach to Power and Ground Routing," Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pp. 6-9, November 1986.
  96. Dai, W-M., M. Sato, and E.S. Kuh, "Partial 3-Trees and Applications to Circuit Layout," Proceedings of IEEE International Symposium on Circuits & Systems, pp. 31-34, May 1987. [SRC, NSF]
  97. Jackson, M.A.B., E.S. Kuh, and M. Marek-Sadowska, "Timing-Driven Routing for Building Block Layout," Proceedings of IEEE International Symposium on Circuits & Systems, pp. 518-519, May 1987. [NSF, JSEP]
  98. Xiong, X-M., and E.S. Kuh, "Nutcracker: An Efficient and Intelligent Channel Spacer," Proceedings of 24th ACM/IEEE Design Automation Conference, pp. 298-304, June 1987. [SRC]
  99. Dai, W-M., M. Sato, and E.S. Kuh, "A Dynamic and Efficient Representation of Building-Block Layout," Proceedings of 24th ACM/IEEE Design Automation Conference, pp. 376-384, June 1987. [SRC, NSF]
  100. Dai, W-M., and E.S. Kuh, "Global Spacing of Building Block Layout," Proceedings of VLSI 1987, pp. 161-174, August 1987. [SRC, NSF]
  101. Dai, W-M., and E.S. Kuh, "Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout," IEEE Trans. on Computer-Aided Design, vol. CAD-6, no. 5, pp. 828-837, September 1987. [SRC, NSF]
  102. Dai, W-M., H. Chen, R. Dutta, M. Jackson, E.S. Kuh, M. Marek-Sadowska, M. Sato, D. Wang, and X-M. Xiong, "BEAR: A New Building-Block Layout System," Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, pp. 34-37, November 1987. [SRC, NSF, JSEP, MICRO]
  103. Tsay, R-S., E.S. Kuh, and C-P. Hsu, "PROUD: A Fast Sea-of-Gates Placement Algorithm," UCB/ERL Memorandum M87/79, November 1987.
  104. Xiong, X-M. and E.S. Kuh, "A Unified Approach to the Via Minization Problem," UCB/ERL Memorandum M87/80, November 1987.
  105. Xu, D-M., Y.K. Chen, E.S. Kuh, and Z.J. Li, "A New Algorithm with Gate Matrix Layout," Proc. IEEE Int. Symp. on Circuits and Systems, pp. 288-291, 1987.
  106. Kuh, E.S., "Opportunities and Challenges in Research and Education for Electrical Engineers," Science and Technology Review, vol. 1, no. 16, pp. 38-41, 1988.
  107. Xiong, X-M., and E.S. Kuh, "The Constrained Via Minimization Problem for PCB and VLSI Designs," Proceedings of 25th Design Automation Conference, pp. 573-578, June 1988. [SRC]
  108. Tsay, R-S., E.S. Kuh, and C-P. Hsu, "PROUD: A Fast Sea-of-Gates Placement Algorithm," Proceedings of 25th Design Automation Conference, pp. 318-323, June 1988. [NSF, JSEP, Hughes]
  109. Cheng, K-T., V.D. Agrawal, and E.S. Kuh, "A Sequential Circuit Test Generator Using Threshold-Value Simulation," Proceedings of 18th Fault Tolerant Computing Symposium, pp. 24-29, June 1988. [NSF, MICRO]
  110. Dai, W-M., and E.S. Kuh, "BEAR: A New Macrocell Layout System for Custom Chip Design," Extended Abstract Volume, SRC Techcon, pp. 45-48, October 1988. [SRC]
  111. Tsay, R-S., E.S. Kuh, and C-P. Hsu, "Module Placement for Large Chips Based on Sparse Linear Equations," International Journal of Circuit Theory and Applications, vol. 16, pp. 411-423, October 1988. [NSF, JSEP, Hughes]
  112. Eschermann, B., W-M. Dai, E.S. Kuh, and M. Pedram, "Hierarchical Placement for Macrocells: A `Meet in the Middle' Approach," Digest of Technical Papers, International Conference on Computer-Aided Design, pp. 460-463, November 1988. [SRC, NSF]
  113. Tsay, R-S., E.S. Kuh, and C-P. Hsu, "PROUD: A Sea-Of-Gates Placement Algorithm," IEEE Design and Test of Computers, pp. 44-56, December 1988. [NSF, JSEP, Hughes]
  114. Xiong, X-M., and E.S. Kuh, "A Unified Approach to the Via Minimization Problem," IEEE Transactions on Circuits and Systems, vol. 36, no. 2, pp. 190-204, February 1989. [SRC]
  115. Spencer, W.J., J.Y. Chen, A. Chiang, W. Frieman, E.S. Kuh, J.L. Moll, R.F. Pease, and K.C. Saraswat, "Chinese Microelectronics," Foreign Applied Sciences Assessment Center Technical Assessment Report, Science Applications International Corporation, April 1989.
  116. Xiong, X-M., and E.S. Kuh, "Geometric Compaction of Building-Block Layout," Proceedings of IEEE Custom Integrated Circuits Conference, pp. 7.6.1-4, May 1989. [SRC]
  117. Jackson, M., and E.S. Kuh, "Performance-Driven Placement of Cell-Baced ICs," Proceedings of 26th Design Automation Conference, pp. 370-375, June 1989. [SRC]
  118. Dai, W. W-M., B. Eschermann, E.S. Kuh, and M. Pedram, "Hierarchial Placement and Floorplanning in BEAR" IEEE Trans. on Computer-Aided Design, pp. 1335-1349, vol. 8, no. 12, December 1989. [SRC, NSF]

  119.  

     

    1990 - 1999
     

  120. Kuh, E.S., and T. Ohtsuki, "Recent Advances in VLSI Layout," IEEE Proceedings Special Issue on Computer-Aided Design, vol. 78, no. 2, pp. 237-263, February 1990. [SRC, NSF, JSEP, JSEP]
  121. Tsay, R-S., and E.S. Kuh, "A Unified Approach to Partitioning and Placement," IBM Research Report RC-15482 (#68859), February 9, 1990. [NSF, MICRO]
  122. Srinivasan, A., and E.S. Kuh, "MOLE -- A Sea-of-Gates Detailed Router," Proceedings of European Design Automation Conference, pp. 446-450, March 1990 [JSEP, NSF]
  123. Jackson, M.A.B., A. Srinivasan, and E.S. Kuh, "A Novel Approach to IC Performance Optimization by Clock Routing," UCB/ERL Memorandum M90/27, April 1990.
  124. Jackson, M.A.B., and E.S. Kuh, "Estimating and Optimizing RC Interconnect Delay During Physical Design," Proceedings of International Symposium on Circuits and Systems, pp. 869-871, May 1990. [NSF, SRC]
  125. Xu, D-M., E.S. Kuh, and Y-K. Chen, "An Extended 1-D Assignment Problem: Net Assignment in Gate Matrix Layout," Proceedings of International Symposium on Circuits and Systems, pp. 1692-1696, May 1990. [NSF]
  126. Ogawa, Y., M. Pedram, and E.S. Kuh, "Timing-Driven Placement for General Cell Layout," Proceedings of International Symposium on Circuits and Systems, pp. 872-876, May 1990. [NSF, SRC]
  127. Jackson, M.A.B., A. Srinivasan, and E.S. Kuh, "Clock Routing for High-Performance ICs," Proceedings of 27th Design Automation Conference, pp. 573-579, June 1990. [SRC, JSEP, NSF]
  128. Lin, S., M. Marek-Sadowska, and E.S. Kuh, "Delay and Area Optimization in Standard-Cell Design," Proceedings of 27th Design Automation Conference, pp. 349-352, June 1990. [MICRO, NSF]
  129. Xiong, Xiao-Ming and E.S. Kuh, "Geometric Approach to VLSI Layout Compaction," International Journal on Circuit Theory and Applications, pp. 411-430, July/August 1990. [SRC]
  130. Kuh, E.S., A. Srinivasan, Michael A.B. Jackson, M. Pedram, Yasushi Ogawa, and M. Marek-Sadowska, "Timing-Driven Layout," Proc. Synthesis and Simulation Meeting and International Interchange, pp. 263-270, October 1990. [SRC, NSF]
  131. Pedram, M., M. Marek-Sadowska, and E.S. Kuh, "Floorplanning with Pin Assignment," Digest of Technical Papers, Int. Conf. on Computer-Aided Design, pp. 98-101, November 1990. [NSF, SRC, MICRO]
  132. Jackson, M., A. Srinivasan, and E.S. Kuh, "A Fast Algorithm for Performance-Driven Placement," Digest of Technical Papers, Int. Conf. on Computer-Aided Design, pp. 328-331, November 1990. [NSF, SRC, JSEP]
  133. Wang, D., and E.S. Kuh, "Novel Routing Schemes for IC Layout Part I: Two-Layer Channel Routing," UCB/ERL Memorandum M90/101, November 1990.
  134. Wang, D., and E.S. Kuh, "Novel Routing Schemes for IC Layout Part II: Three-Layer Channel Routing," UCB/ERL Memorandum M90/102, November 1990.
  135. Cheng, Kwang-Ting, Vishwani D. Agrawal, and E.S. Kuh, "A Simulation-Based Method for Generating Tests for Sequential Circuits," IEEE Trans. on Computers, Vol. 39, No. 12, pp. 1456-1463, December 1990. [NSF, MICRO]
  136. Lin, S., M. Marek-Sadowska, and E.S. Kuh, "SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits," pp. 142-148, Proc. European Design Automation Conference, February 1991. [NSF, MICRO]
  137. Pedram, M., N. Bhat, K. Chaudhary, and E.S. Kuh, "Layout Considerations in Combinational Logic Synthesis," Proc. International Workshop on Logic Synthesis," May 1991. [NSF, SRC]
  138. Srinivasan, A., K. Chaudhary, and E.S. Kuh, "RITUAL: Performance-Driven Placement of Cell-Based ICs," Proc. 3rd Physical Design Workshop, May 1991. [NSF, SRC]
  139. Tsay, R-S. and Ernest Kuh, "A Unified Approach to Partitioning and Placement," IEEE Trans. on Circuits and Systems, Vol. CAS-38, No. 5, pp. 521-533, May 1991.
  140. Xu, D-M., E.S. Kuh, and Y-K. Chen, "An Array Optimization Algorithm for VLSI Layout," Proc. International Conf. on Circuits and Systems, Shenzhen, China, June 1991.
  141. Lin, S., and E.S. Kuh, "A New Approach to Circuit Simulation," Proc. European Conf. on Circuit Theory and Design, pp. 264-273, September 1991. [NSF, MICRO]
  142. Shih, M., E.S. Kuh, and R-S. Tsay, "Performance-Driven System Partitioning on Multi-Chip Modules," IBM Research Division Research Report RC 17315 (#76556), October 1991.
  143. Wang, D., and E.S. Kuh, "New Algorithms for 2-Layer and 3-Layer Channel Routing," Int. Journal of Circuit Theory and Applications, Vol. 19, No. 6, pp. 525-549, November/December 1991.
  144. Pedram, M., K. Chaudhary, and E.S. Kuh, "I/O Pad Assignment Based on the Circuit Structure," Proc. ICCD, October 1991.
  145. Srinivasan, A., K. Chaudhary, and E.S. Kuh, "RITUAL: A Performance Driven Placement Algorithm for Small Cell ICs," Proc. Int. Conf. on Computer-Aided Design, pp. 48-51, November 1991.
  146. Srinivasan, A., K. Chaudhary, and E.S. Kuh, "RITUAL: A Performance Driven Placement Algorithm," UCB/ERL Memorandum M91/103, November 1991.
  147. Lin, S., E.S. Kuh, and M. Marek-Sadowska, "A New Accurate and Efficient Timing Simulator," Proc. VLSI Design Conference, January 1992.
  148. Lin, S., and E.S. Kuh, "Pade Approximation Applied to Transient Simulation of Lossy Coupled Transmission Lines," Proc. IEEE Multi-Chip Module Conference, pp. 52-55, March 1992. [SRC]
  149. Pedram, M., and E.S. Kuh, "BEAR-FP: A Robust Framework for Floorplanning," Int. Journal of High Speed Electronics, Vol. 3, No. 1, pp. 137-170, March 1992. [NSF, SRC]
  150. Shih, M., E.S. Kuh, and R-S. Tsay, "System Partitioning for Multi-Chip Modules Under Timing and Capacity Constraints," Proc. IEEE Multi-Chip Module Conference, pp. 123-126, March 1992. [NSF, SRC]
  151. Lin, S., and E.S. Kuh, "Pade Approximation Applied to Lossy Transmission Line Circuit Simulation," Proc. Int. Symposium on Circuits and Systems, pp. 93-96, May 1992.
  152. Hong, X-L., J. Huang, C-K. Cheng, and E.S. Kuh, "FARM: An Efficient Feed-Through Pin Assignment Algorithm," Proc. Design Automation Conference, pp. 530-535, June 1992. [NSF]
  153. Lin, S., and E.S. Kuh, "Transient Simulation of Lossy Interconnect," Proc. Design Automation Conference, pp. 81-86, June 1992. [SRC]
  154. Mitsuhashi, T., and E.S. Kuh, "Power and Ground Network Topology Optimization for Cell-Based VLSIs," Proc. Design Automation Conference, pp. 524-529, June 1992
  155. Shih, M., E.S. Kuh, and R-S. Tsay, "Performance-Driven Partitioning on Multi-Chip Modules," Proc. Design Automation Conference, pp. 53-56, June 1992. [NSF, SRC]
  156. Lin, S. and E.S. Kuh, "Transient Simulation of Lossy Coupled Transmission Lines," Proc. European Design Automation Conference, pp. 126-131, September 1992. [SRC]
  157. Lin, S., and E.S. Kuh, "Transient Simulation of Lossy Interconnects Based on the Recursive Convolution Formulation," IEEE Trans. on Circuits and Systems -- I: Fund. Theory and Applications, Vol. 39, No. 11, pp. 879-892, November 1992. [SRC]
  158. Srinivasan, A., Chaudhary, K., and E.S. Kuh, "RITUAL: A Performance-Driven Placement Algorithm," IEEE Trans. on Circuits and Systems--II: Analog and Digital Signal Processing, Vol. 39, No. 11, pp. 825-840, November 1992. [SRC, NSF]
  159. Kuh, E.S. and M. Shih, "Recent Advances in Timing-Driven Physical Design," Proc. IEEE Asia-Pacific Conference on Circuits and Systems, pp. 23-28, December 1992.
  160. Shih, M., E.S. Kuh, and R-S. Tsay, "Integer Programming Techniques for Multiway System Partitioning Under Timing and Capacity Constraints," Proc. EDAC-Euroasic Conf., February 1993.
  161. Shih, M., E.S. Kuh, and R-S. Tsay, "Timing-Driven System Partitioning by Constraints Decoupling Method," Proc. 1993 IEEE Multichip Module Conf., pp. 164-169, March 1993. [SRC]
  162. Shih, M., and E.S. Kuh, "Quadratic Boolean Programming For Performance-Driven System Partitioning," UCB/ERL Memorandum M93/19, March 1993.
  163. Lin, S. , E.S. Kuh, and M. Marek-Sadowska, "Stepwise Equivalent Conductance Circuit Simulation Technique," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems," Vol. 12, No. 5, pp. 672-683, May 1993.
  164. Hong, X., T. Xue, J. Huang, E.S. Kuh, and C-K. Cheng, "Performance-driven Steiner Tree Algorithms for Global Routing," Proc. 30th Design Automation Conf., pp. 177-181, June 1993.
  165. Huang, J., X. Hong, C-K. Cheng, and E.S. Kuh, "An Efficient Timing-Driven Global Routing Algorithm," Proc. 30th Design Automation Conf., pp. 596-600, June 1993.
  166. Shih, M., and E.S. Kuh, "Quadratic Boolean Programming for Performance-Driven System Partitioning," Proc. 30th Design Automation Conf., pp. 761-765, June 1993.
  167. Bhat, N., K. Chaudhary, and E.S. Kuh, "Performance-Oriented Fully Routable Dynamic Architecture for a Field-Programmable Logic Device," UCB/ERL Memorandum M93/42, June 1993.
  168. Lin, S., and E.S. Kuh, "Fast and Accurate Simulation of Large Lossy Interconnect Networks Using Circuit Partition and Recursive Convolution," Proc. European Conf. on Circuit Theory and Design, pp. 1549-1553, August 1993.
  169. Shih, M. and E.S. Kuh, "Timing-Driven System Partitioning by Generalized Burkard's Heuristic," Proc. European Conf. on Circuit Theory and Design, pp. 1543-1548, August 1993. [SRC]
  170. Lin, S. and E.S. Kuh, "Circuit Simulation for Large Interconnected IC Networks," Proc. VLSI 93, pp. 9.1.1-10, September 1993.
  171. Xue, T., T. Fujii, and E.S. Kuh, "A New Performance-Driven Global Routing Algorithm for Gate Array," Proc. VLSI 93, pp. 8.3.1-10, September 1993.
  172. Shih, M., and E.S. Kuh, "Technology-Driven Circuit Partitioning," Extended Abstract Volume, SRC Techcon '93, pp. 207-209, September 1993.
  173. Chaudhary, K., A. Onozawa, and E.S. Kuh, "A Spacing Algorithm for Performance Enhancement and Cross-talk Reduction," Digest of Technical Papers, IEEE/ACM Int. Conf. on CAD, pp. 697-702, November 1993.
  174. Shih, M., and E.S. Kuh, "Quadratic Boolean Programming for Performance-Driven System Partitioning," UCB/ERL Memorandum M93-19, March 1993 (Revised 23 November 1993).
  175. Yu, Q., and E.S. Kuh, "Moment Models of General Transmission Lines with Application to Interconnect Analysis," Proceedings of the IEEE Multi-Chip Module Conference MCMC 95, pp. 152-157, January, 1995.
  176. Lin, Shen and Ernest S. Kuh, "SWEC Speeds VLSI Simulations," IEEE Circuits and Devices, Vol. 11, No. 1, pp. 10-15, January 1995.
  177. * Buch, P., Lin, S., Nagasamy, V., and E.S. Kuh, "Techniques for Fast Circuit Simulation Applied to Power Estimation of CMOS Circuits," Proceedings of the 1995 International Symposium on Low Power Design, pp. 135-138, April 1995.
  178. * Hough, C., Xue, T., and E.S. Kuh, "New Approaches for On-Chip Power Switching Noise Reduction," Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 133-136, May, 1995.
  179. Onozawa, A., Chaudhary, K., and E.S. Kuh, "Performance Driven Spacing Algorithms Using Attractive and Repulsive Constraints for Submicron LSI's," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 6, pp. 707-719, June 1995.
  180. Yu, Q., and E.S. Kuh, "Moment Matching Model of Transmission Lines and Application to Interconnect Delay Estimation," IEEE Transactions on VLSI Systems, Vol. 3, No. 2, pp. 311-322, June, 1995.
  181. Dongmin, X., Chen, Y.K., and E.S. Kuh, "An Array Optimization Algorithm for VLSI Layout," Journal of Tsinghua University (Sci & Tech), Vol. 35, No. 1, pp. 1-9, 1995.
  182. Xue, T., and E.S. Kuh, "Post Routing Performance Optimization via Multi-Link Insertion and Non-Uniform Wiresizing," Proceedings of the ICCAD '95, San Jose, CA, November 5-9, 1995, pp. 575-580.
  183. Wang, D.S., and E.S. Kuh, "Performance-Driven Interconnect Global Routing," Proceedings of the 1996 Great Lakes Symposium on VLSI, pp. 132-136, March, 1996.
  184. Yu, Q. and Ernest S. Kuh, "An Accurate Time Domain Interconnect Model of Transmission Line Networks," IEEE Transactions on Circuits and Systems, Vol. 43, No. 3, pp. 200-208, March 1996.
  185. Xue, T, Yu, Q., and E.S. Kuh, "A Sensitivity-Based Wiresizing Approach to Interconnect Optimization of Lossy Transmission Line Topologies," Proceedings of the 1996 IEEE Multi-Chip Module Conference, pp. 117-121, February, 1996.
  186. Esbensen, H., and E.S. Kuh, "An MCM/IC Timing-Driven Placement Algorithm Featuring Explicit Design Space Exploration," Proceedings of the 1996 IEEE Multi-Chip Module Conference, pp. 170-175, February, 1996.
  187. Esbensen, H., and E.S. Kuh, "Design Space Exploration Using the Genetic Algorithm," Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, pp. 500-503, May, 1996.
  188. Esbensen, H., and E.S. Kuh, "Explorer: An Interactive Floorplanner for Design Space Exploration," Proc. Euro-DAC'96, pp. 356-361, September 1996.
  189. Xue, T., E.S. Kuh, and D.S. Wang, "Post Global Routing Crosstalk Risk Estimation and Reduction," Proceedings of the IEEE/ACM Int'l Conf. on Computer-Aided Design, pp. 302-309, November, 1996.
  190. Mao, J-M., J.M. Wang, and E.S. Kuh, "Simulation and Sensitivity Analysis of Transmission Line Circuits by the Characteristics Method," ICCAD'96, pp. 556-562, November, 1996.
  191. Yu, Q., E.S. Kuh and T. Xue, "Moment Models of General Transmission Line with Application to Interconnect Analysis and Optimization," IEEE Trans. on VLSI Systems, Vol. 4, No. 4, pp. 477-494, December, 1996.
  192. Buch, P., and E.S. Kuh, "Symphony: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits," Proceedings of the 10th International Conference on VLSI Design '97, pp. 403-407, January, 1997.
  193. Esbensen, H., and E.S. Kuh, "A Performance-Driven IC/MCM Placement Algorithm Featuring Explicit Design Space Exploration," ACM Transactions on Design Automation of Electronic Systems, pp. 62-80, January 1997.
  194. Wang, D.S., E.S. Kuh, "A New Timing-Driven Multilayer MCM/IC Routing Algorithm," Proc. MCMC'97, pp. 89-94, February, 1997.
  195. Mao, J.-F., and E.S. Kuh, "Fast Simulation and Sensitivity Analysis of Lossy Transmission Lines by the Method of Characteristics," IEEE Transactions on Circuits and Systems, pp. 391-401, May 1997.
  196. Yu, Q., and E.S. Kuh, "Reduced order model of transmission lines with preservation of passivity and moment matching at multiple points," 1997 Intl. Symp. on Nonlinear Theory and its Applications (NOLTA'97), pp. 845-848, Nov. 1997.
  197. Hong, X., T. Xue, J. Huang, C.K. Cheng, and E.S. Kuh, "TIGER: An Efficient Timing - Driven Global Router for Gate Array and Standard Cell Layout-Design," IEEE Trans. Computer-Aided Design, Vol. 16, No. 11, pp. 1323-1331, Nov. 1997.
  198. Wang, D.S., and E.S. Kuh, "Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction," to appear in Proceeding of Euro-DAC'98.
  199. Kuh, E.S., "Emerging DSM Interconnect Tools, and interview with Prof. Ernest S. Kuh," Integrated System Design-Electronics Journal, pp. 23-25, Dec. 1997.
  200. Murata, H., E.S. Kuh, "Sequence-Pair Based Placement Method for Hard/Soft/Pre-placed Modules," ISPD'98, pp. 167-172.
  201. Yu, Q., J.M. Wang, and E.S. Kuh, "Reduced order model of RLC interconnects with multi-point moment matching and passivity preservation," ISCAS'98, Vol. VI, pp. 74-77, 1998.
  202. Wang, D. and E.S. Kuh, "A New General Connectivity Model and Its Applications to Timeing-Driven Steiner Tree Routing," 1998 IEEE International Conference on Electronic Circuits and Systems 72-72, 1998.
  203. Yu, Q., Wang, J., and E.S. Kuh, "Multipoint Moment Matching Model for Multiport Distributed Interconnect, " IEEE/ACM International Conference on Computer-Aided Design, pp.85-91, Nov. 1998.
  204. Yu, Q., J.M. Wang, and E.S. Kuh, "Passive Multipoint Moment Model Order Reduction Algorithm on Multiport Distributed Interconnect Networks, " IEEE Trans. Ciruits and Systems, I, Vol.46, No. 1 pp. 140-160, January, 1999.
  205. J.M. Wang, Q. Yu, and E.S. Kuh, "Coupled Noise Estimation for Distributed RC Interconnect Model," in Proceedings DATE 1999, pp. 664-668.
  206. J.M. Wang,  E.S. Kuh and Qingjian Yu, "The Chebyshev expansion based passive model for distributed interconnect networks,” Proceedings  ICCAD 99, pp 370-375.
  207. 2000 - Present
     

  208. Pinhong Chen and Ernest S. Kuh, "Floorplan Sizing by Linear Programming Approximation,”  Proceedings 37th Design Automation Conference, pp 468-472, June 2000.
  209. Qingjian Yu, J.M Wang and Ernest S. Kuh, "Passive Model Order Reduction Algorithm based on Chebyshev Expansion of Impulsive Response of Interconnect Networks,”  Proceedings 37th Design Automation Conference, pp 520-525, June, 2000.
  210. J. M. Wang, and E.S. Kuh, “Recent Development in Interconnect Modeling,” Interconnects in VLSI Design Kluwer Academic Publications pp. 1-23, 2000.
  211. E.S. Kuh, “Circuit Theory and Interconnect Analysis for DSM Chip Design,” Proceedings IEEE Asia Pacific Conterence on Circuits and Systems, pp. 1-3, December, 2000.
  212. E.S. Kuh and O.J. Yu, "Explicit formulas and Efficient Algorithm for Moment Computation of Coupled RC Trees," Proc. DATE, pp. 445-450, March 12, 2001.
  213. E.S. Kuh, "Recent Advance on Circuit and Interconnect Simulation for Deep Submicron IC Design," Proc. Signal Propagation in Interconnect, May 13, 2001.
  214. E.S. Kuh and Q.J. Yu, "Moment Computation of Lumped and Distributed Coupled RC Trees with Application to Delay and Crosstalk Estimation," Proc. IEEE, Vol. 89, No.5, pp. 772-788, May, 2001.
  215. E.S. Kuh and Q.J. Yu, "New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees," Proc. Quality Electronic Design, pp. 151-157, 2001.
  216. E.S. Kuh and Q.J. Yu, "Passive Time-Domain Model Order Reduction via Orthonormal Basis Fruitions," Proc. 15th European Conf. on Circuit Theory and Design, Vol. III, pp. 37-40, 2001.
  217. J.M. Wang, C. Chu, Q. Yu, and E. S. Kuh, "On Projection-Based Algorithms for Model-Order Reduction of Interconnects," IEEE Trans. Circuits and Systems, Part I, Vol. 49, No. 11, pp 1563-1585, Nov. 2002.
  218. E.S. Kuh and Chi-Ping Hsu, "Physical Design Overview," The Best of ICCAD, Kluwer Acad. Publishers, pp 467-477, 2003.
  219. I.W. Sandberg and Ernest S. Kuh, "Sidney Darlington 1906-1997," National Academy of Sciences, Biographical Memoirs, Vol. 84.
  220. Z. Zhu, K. Rouz, M. Borah, C.K. Cheng, and E.S. Kuh, "Efficient Transient Simulation for Transistor-Level Analysis," ASP-DAC, pp. 240-243, 2005.
  221. H. Zhu, C. K. Cheng, Rouz, Borah, and Ernest S. Kuh, "Two-Stage Newton-Raphson Method fro Transistor-Level Simulation," Trans. IEEE on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.5, May 2007, pp 881-893.
  222. L. Zhang, W. Yu, H. Zhu, A. Deutsch, G. Katopis, D. Dreps, E.S. Kuh, and C.K. Cheng, "Low Power Passive Equalizer Optimization using Tritonic Step Response," IEEE/ACM Design Automation Conf. 2008.
  223. R. Shi, W. Yu, C.K. Cheng, E.S. Kuh, "Efficient and Accurate Eye Diagram Prediction for High Speed Signaling," ACM/IEEE Int. Conf. on Computer-Aided Design, 2008.
Last updated 03/19/07