Krste Asanović, Publications by Year

Many of these papers are copyright of the respective journal or conference organizing body. These online copies are provided for your personal research use only.

• Publications organized by type

2013

• Henry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David Patterson, Krste Asanović, "A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness", To Appear, International Symposium on Computer Architecture (ISCA-2013), Tel Aviv, Israel, June 2013.

• Juan A. Colmenares, Gage Eads, Steven Hofmeyr, Sarah Bird, Miquel Moretó, David Chou, Brian Gluzman, Eric Roman, Davide B. Bartolini, Nitesh Mor, Krste Asanović, John D. Kubiatowicz, "Tessellation: Refactoring the OS around Explicit Resource Containers with Continuous Adaptation", To Appear, Design Automation Conference (DAC-2013), Austin, TX, June 2013.

• Scott Beamer, Aydın Buluç, Krste Asanović, David Patterson, "Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search", To Appear, Workshop on Multithreaded Architectures and Applications (MTAAP-2013), at the International Parallel & Distributed Processing Symposium (IPDPS-2013), Boston, May 2013.

• Yunsup Lee, Ronny Krashinsky, Vinod Grover, Stephen W. Keckler, Krste Asanović, "Convergence and Scalarization for Data-Parallel Architectures", International Symposium on Code Generation and Optimization (CGO 2013), Shenzhen, China, February 2013. PDF

• Christopher Batten, Ajay Joshi, Vladimir Stojanović, and Krste Asanović, "Designing Chip-Level Nanophotonic Interconnection Networks", Chapter in Integrated Optical Interconnect Architectures and Applications in Embedded Systems, Gabriela Nicolescu and Ian O'Connor (Editors), Springer, ISBN 978-1-4419-6192-1, 2013. [Extended version of JETCAS paper.] link

2012

• Brian Zimmer, Seng Oon Toh, Huy Vo, Yunsup Lee, Olivier Thomas, Krste Asanović, and Borivoje Nikolić, "SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS", IEEE Transactions on Circuits and Systems-II, 59(12), December 2012. PDF

• Scott Beamer, Krste Asanović, David Patterson, "Direction-Optimizing Breadth-First Search", International Conference for High Performance Computing, Networking, Storage, and Analysis (SC12), Salt Lake City, UT, November 2012.
  Best Student Paper Finalist PDF

• Jae W. Lee, Man Cheuk Ng, and Krste Asanović, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks", Journal of Parallel and Distributed Computing, 72(11), November 2012. PDF

• Mohit Tiwari, Prashanth Mohan, Andrew Osheroff, Hilfi Alkaff, Elaine Shi, Eric Love, Dawn Song, Krste Asanović, "Context-centric Security", 7th Usenix Workshop on Hot Topics in Security (HotSec'12), Bellevue, WA, August 2012. PDF

• Christopher Batten, Ajay Joshi, Vladimir Stojanović, and Krste Asanović, "Designing Chip-Level Nanophotonic Interconnection Networks", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2012. PDF

• Martin Maas, Philip Reames, Jeffrey Morlan, Krste Asanović, Anthony D. Joseph, John Kubiatowicz, "GPUs: An Opportunity for Offloading Garbage Collection", International Symposium on Memory Management (ISMM-2012), Beijing, China, June 2012. PDF

• Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, Krste Asanović, "Chisel: Constructing Hardware in a Scala Embedded Language", Design Automation Conference (DAC-2012), San Francisco, CA, June 2012. PDF

• Theses Supervised:
  • Brian Zimmer, "Resilient Design Methodology for Energy-Efficient SRAM"
    M.S. Thesis, University of California, Berkeley, May 2012. PDF

2011

• Scott Beamer, Krste Asanović, and David Patterson, "Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500", Technical Report UCB/EECS-2011-117, EECS Department, University of California, Berkeley, November 2011. PDF

• Juan Colmenares, Ian Saxton, Eric Battenberg, Rimas Avižienis, Nils Peters, Krste Asanović, John Kubiatowicz, and David Wessel, "Real-time musical applications on an experimental operating system for multi-core processors", 2011 International Computer Music Conference (ICMC-2011), Huddersfield, England, July 2011. PDF

• Yunsup Lee, Rimas Avižienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanović, "Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators", International Symposium on Computer Architecture (ISCA-2011), San Jose, CA, June 2011. PDF

• Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA", Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 2011. PDF

• Zhangxi Tan, Krste Asanović, and David A. Patterson, "Datacenter-Scale Network Research on FPGAs", The Exascale Evaluation and Research Techniques Workshop (EXERT 2011), at the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2011), Newport Beach, CA, March 2011. PDF

• Theses Supervised:
  • Rimas Avižienis, "The Case for User-Level Preemptive Scheduling to Support Multi-Rate Audio Applications for Multi-Core Processors"
    M.S. Thesis, University of California, Berkeley, December 2011. PDF
  • Yunsup Lee, "Efficient VLSI Implementations of Vector-Thread Architectures"
    M.S. Thesis, University of California, Berkeley, December 2011. PDF
  • Andrew S. Waterman, "Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed"
    M.S. Thesis, University of California, Berkeley, May 2011. PDF

2010

• Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanović, David A. Patterson, "A Case for FAME: FPGA Architecture Model Execution", International Symposium on Computer Architecture (ISCA-2010), Saint-Malo, France, June 2010. PDF

• Scott Beamer, Chen Sun, Yong-jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanović, Krste Asanović, "Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics", International Symposium on Computer Architecture (ISCA-2010), Saint-Malo, France, June 2010. PDF

• Juan A. Colmenares, Sarah Bird, Henry Cook, Paul Pearce, David Zhu, John Shalf, Krste Asanović, and John Kubiatowicz, "Resource Management in the Tessellation Manycore OS", 2nd USENIX Workshop on Hot Topics in Parallelism (HotPar '10), Berkeley, CA, June 2010. PDF

• Zhangxi Tan, Andrew Waterman, Rimas Avižienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanović, "RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors", Design Automation Conference (DAC-2010), Anaheim, CA, June 2010. PDF

• Heidi Pan, Benjamin Hindman, and Krste Asanović, "Composing Parallel Software Efficiently with Lithe", Programming Language Design and Implementation (PLDI-2010), Toronto, Canada, June 2010. PDF

• Vladimir Stojanović, Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Chen Sun, Krste Asanović, "Design-Space Exploration for CMOS Photonic Processor Networks", Optical Fiber Communication Conference and Exposition and The National Fiber Optic Engineers Conference (OFC/NFOEC), San Diego, CA, March 2010.
  Invited paper. PDF

• Zhangxi Tan, Krste Asanović, and David A. Patterson, "An FPGA-Based Simulator for Datacenter Networks", The Exascale Evaluation and Research Techniques Workshop (EXERT 2010), at the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), Pittsburgh, PA, March 2010. PDF

• Theses Supervised:
  • Heidi Pan, "Cooperative Hierarchical Resource Management for Efficient Composition of Parallel Software"
    Ph.D. Thesis, Massachusetts Institute of Technology, June 2010. PDF
  • Christopher F. Batten, "Simplified Vector-Thread Architectures for Flexible and Efficient Data-Parallel Accelerators"
    Ph.D. Thesis, Massachusetts Institute of Technology, February 2010. PDF

  • Sarah Bird, "Software Knows Best: A Case for Hardware Transparency and Measurability"
    M.S. Thesis, University of California, Berkeley, May 2010. PDF
  • Yong-jin Kwon, "Parameterized DRAM Model"
    M.S. Thesis, University of California, Berkeley, May 2010. PDF

2009

• Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanović, and Vladimir Stojanović, "Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics", Workshop on Photonic Interconnects & Computer Architecture (PICA), at the 42nd ACM/IEEE International Symposium on Microarchitecture (MICRO-42), New York, NY, December 2009. PDF

• Krste Asanović, Rastislav Bodik, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, and Katherine Yelick, "A View of the Parallel Computing Landscape", Communications of the ACM, October 2009. PDF

• John Shalf, Krste Asanović, David A. Patterson, Kurt Keutzer, Tim Mattson, and Katherine Yelick, "The Manycore Revolution: Will the HPC Community Lead or Follow?", SciDAC Review, Fall 2009. PDF

• Bryan Catanzaro, Shoaib Kamil, Yunsup Lee, Krste Asanović, James Demmel, Kurt Keutzer, John Shalf, Kathy Yelick, Armando Fox, "SEJITS: Getting Productivity AND Performance With Selective Embedded JIT Specialization", First Workshop on Programming Models for Emerging Architectures (PMEA), at the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, NC, September 2009. PDF
  Also available as UCB Technical Report UCB/EECS-2010-23.

• Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kärtner, Rajeev Ram, Vladimir Stojanović, and Krste Asanović, "Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics", IEEE Micro, July/August 2009. PDF

• Scott Beamer, Krste Asanović, Christopher Batten, Ajay Joshi, and Vladimir Stojanović, "Designing Multi-socket Systems Using Silicon Photonics", 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, NY, June 2009. (ACM DL) PDF

• Vladimir Stojanović, Ajay Joshi, Christopher Batten, Yong-Jin Kwon, and Krste Asanović, "Manycore processor networks with monolithic integrated CMOS photonics", 29th Conference on Lasers and Electro-Optics (CLEO'09), Baltimore, MD, June 2009. PDF
  Invited paper.

• Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanović and Vladimir Stojanović, "Silicon-Photonic Clos Networks for Global On-Chip Communication", 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS), San Diego, CA, May 2009. PDF

• Christopher Grant Jones, Rose Liu, Leo Meyerovich, Krste Asanović, and Rastislav Bodik, "Parallelizing the Web Browser", First USENIX Workshop on Hot Topics in Parallelism (HotPar'09), Berkeley, CA, March 2009. PDF

• Rose Liu, Kevin Klues, Sarah Bird, Steven Hofmeyr, Krste Asanović, and John Kubiatowicz, "Tessellation: Space-Time Partitioning in a Manycore Client OS", First USENIX Workshop on Hot Topics in Parallelism (HotPar'09), Berkeley, CA, March 2009. PDF

• Heidi Pan, Benjamin Hindman, and Krste Asanović, "Lithe: Enabling Efficient Composition of Parallel Libraries", First USENIX Workshop on Hot Topics in Parallelism (HotPar'09), Berkeley, CA, March 2009. PDF

• Theses Supervised:
  • Jae W. Lee, "Globally Synchronized Frames for Guaranteed Quality-of-Service in Shared Memory Systems"
    Ph.D. Thesis, Massachusetts Institute of Technology, September 2009. PDF

  • Henry M. Cook, "Virtualizing Local Stores"
    M.S. Thesis, University of California, Berkeley, December 2009. PDF
  • Scott Beamer, "Designing Multisocket Systems with Silicon Photonics"
    M.S. Thesis, University of California, Berkeley, December 2009. PDF

2008

• Christopher Batten, Hidetaka Aoki, and Krste Asanović, "The Case for Malleable Stream Architectures", Workshop on Streaming Systems at 41st International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, November 2008. PDF

• Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Miloš Popović, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kärtner, Rajeev Ram, Vladimir Stojanović, and Krste Asanović, "Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics", 16th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, CA, August 2008. PDF

• Daniel Burke, John Wawrzynek, Krste Asanović, Alex Krasnov, Andrew Schultz, Greg Gibeling, Pierre-Yves Droz, "RAMP Blue: Implementation of a Multicore 1008 Processor FPGA System", Reconfigurable Systems Summer Institute, Urbana, IL, July 2008. PDF

• Ronny Krashinsky, Christopher Batten, and Krste Asanović, "Implementing the Scale Vector-Thread Processor", ACM Transactions on Design Automation of Electronic Systems (TODAES), 13(3), 41:1-41:24, July 2008. PDF

• Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanović, "System and method for performing memory operations in a computing system", US Patent 7,398,359, issued July 2008. PDF

• Zhangxi Tan, Krste Asanović, and David A. Patterson, "An FPGA Host-Multithreaded Functional Model for SPARC v8", 3rd Workshop on Architectural Research Prototyping (WARP-2008), at 35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008. PDF

• Jae W. Lee, Man Cheuk Ng, and Krste Asanović, "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks", 35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008. PDF

• Mark Hampton and Krste Asanović, "Compiling for Vector-Thread Architectures", International Symposium on Code Generation and Optimization (CGO-2008), Boston, MA, April 2008. PDF

• Krste Asanović, Ras Bodik, James Demmel, Tony Keaveny, Kurt Keutzer, John D. Kubiatowicz, Edward A. Lee, Nelson Morgan, George Necula, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel and Katherine A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View", Technical Report UCB/EECS-2008-23, EECS Department, University of California, Berkeley, March 2008. PDF

• Theses Supervised:
  • Mark J. Hampton, "Reducing Exception Management Overhead with Software Restart Markers"
    Ph.D. Thesis, Massachusetts Institute of Technology, February 2008. PDF

  • Carrell D. Killebrew, "L2 Cache to Off-chip Memory Networks for Chip Multiprocessors"
    M.S. Thesis, University of California, Berkeley, May 2008. PDF
  • Asif I. Khan, "Emulation of Microprocessor Memory Systems Using the RAMP Design Framework"
    S.M. Thesis, Massachusetts Institute of Technology, February 2008. PDF

2007

• Krste Asanović, "Vector Processing", Chapter in The Computer Engineering Handbook, Second Edition: Digital Systems and Applications, editor Vojin G. Oklobdžija, CRC Press, Taylor and Francis Group, ISBN 9780849386190, November 2007.

• Krste Asanović, "Transactors for Parallel Hardware and Software Co-Design", IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007), Irvine, CA, November 2007. PDF
  Invited paper.

• Krste Asanović and Emmett Witchel, "System and technique for fine-grained computer memory protection", US Patent 7,287,140, issued October 2007. PDF

• Jae W. Lee, Myron King, and Krste Asanović, "Continual Hashing for Efficient Fine-Grain State Inconsistency Checking", IEEE International Conference on Computer Design (ICCD-2007), Lake Tahoe, CA, October 2007. PDF
  

• Seongmoo Heo, Ronny Krashinsky, and Krste Asanović, "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy", IEEE Transactions on VLSI Systems, 15(9), September 2007. PDF
  

• John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos Kozyrakis, James C. Hoe, Derek Chiou, and Krste Asanović, "RAMP: Research Accelerator for Multiple Processors", IEEE Micro 27(2), March/April 2007. PDF
  

• Ronny Krashinsky, Christopher Batten, and Krste Asanović, "The Scale Vector-Thread Processor",
  Winner, DAC/ISSCC Student Design Contest, February/June 2007.

• Christopher Batten, Ronny Krashinsky, and Krste Asanović, "Scale Control Processor Test-Chip", Technical Report MIT-CSAIL-TR-2007-003, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, January 2007. PDF

• Theses Supervised:
  • Ronny Krashinsky, "Vector-Thread Architecture and Implementation"
    Ph.D. Thesis, Massachusetts Institute of Technology, May 2007. PDF
    Winner, George M. Sprowls Award for best Ph.D. thesis in Computer Science, MIT, 2007.

2006

• Krste Asanović, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams and Katherine A. Yelick, "The Landscape of Parallel Computing Research: A View from Berkeley", Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley, December 2006. PDF

• Stephen Crago, Janice Onanian McMahon, Chris Archer, Krste Asanović, Richard Chaung, Keith Goolsbey, Mary Hall, Christos Kozyrakis, Kunle Olukotun, Una-May O'Reilly, Rick Pancoast, Viktor Prasanna, Rodric Rabbah, Steve Ward, Donald Yeung, "CEARCH: Cognition Enabled Architecture", Proceedings of the 10th Workshop on High Performance Embedded Computing (HPEC), Lexington, MA, September 2006. PDF

• Jessica Tseng and Krste Asanović, "RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture", Technical Report MIT-CSAIL-TR-2006-066, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, September 2006. PDF

• Krste Asanović, John Hennessy, David A. Patterson, "Vector Processors", Appendix F in Computer Architecture: A Quantitative Approach, Fourth Edition, Morgan Kaufman, ISBN 0-12-370490-1, September 2006.

• Kenneth C. Barr and Krste Asanović, "Energy-Aware Lossless Data Compression", ACM Transactions on Computer Systems, 24(3):250-291, August 2006.

• David A. Patterson, Arvind, Krste Asanović, Derek Chiou, James C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan Rabaey, and John Wawrzynek, "RAMP: Research Accelerator for Multiple Processors", Hot Chips 18, Stanford, CA, August 2006. PDF

• Vern Paxson, Krste Asanović, Sarang Dharmapurikar, John W. Lockwood, Ruoming Pang, Robin Sommer, Nicholas C. Weaver, "Rethinking Hardware Support for Network Analysis and Intrusion Prevention", 1st Workshop on Hot Topics in Security (HotSec'06), Vancouver, Canada, July 2006. PDF

• Mark Hampton and Krste Asanović, "Implementing Virtual Memory in a Vector Processor with Software Restart Markers", 20th ACM International Conference on Supercomputing (ICS06), Cairns, Australia, June 2006. PDF

• Jae W. Lee and Krste Asanović, "METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors", 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), San Jose, CA, April 2006. PDF

• Rose F. Liu and Krste Asanović, "Accelerating Architectural Exploration Using Canonical Instruction Segments", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006. PDF

• Kenneth C. Barr and Krste Asanović, "Branch Trace Compression for Snapshot-Based Simulation", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2006), Austin, TX, March 2006. PDF

• Greg Gibeling, Andrew Schultz, and Krste Asanović, "The RAMP Architecture & Description Language", 2nd Workshop on Architecture Research using FPGA Platforms (WARFP-2006), at 12th International Symposium on High Performance Computer Architecture (HPCA-12), Austin, Texas, February 2006. PDF

• C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, "Unbounded Transactional Memory", IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences, January/February 2006. PDF
  

• Theses Supervised:
  • Kenneth C. Barr, "Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots"
    Ph.D. Thesis, Massachusetts Institute of Technology, August 2006. PDF
  • Jessica H. Tseng, "Banked Microarchitectures for Complexity-Effective Superscalar Microprocessors"
    Ph.D. Thesis, Massachusetts Institute of Technology, May 2006. PDF
  • Albert Ma, "Circuits for High-Performance Low-Power VLSI Logic"
    Ph.D. Thesis, Massachusetts Institute of Technology, May 2006. PDF
  • Michael Zhang, "Latency Reduction Techniques for Chip Multiprocessor Cache Systems"
    Ph.D. Thesis, Massachusetts Institute of Technology, January 2006. PDF
  • Seongmoo Heo, "Optimal Digital System Design in Deep Submicron Technology"
    Ph.D. Thesis, Massachusetts Institute of Technology, January 2006. PDF

2005

• Emmett Witchel, Junghwan Rhee, Krste Asanović, "Mondrix: Memory Isolation for Linux using Mondriaan Memory Protection", 20th ACM Symposium on Operating Systems Principles (SOSP-20) Brighton, UK, October 2005. PDF

• Michael Zhang and Krste Asanović, "Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches", Technical Report MIT-CSAIL-TR-2005-064, Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, October 2005. PDF

• Arvind, Krste Asanović, Derek Chiou, James C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, David A. Patterson, Jan Rabaey, and John Wawrzynek, "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform", Technical Report UCB/CSD-05-1412, CS Division, University of California, Berkeley, September 2005. PDF

• Heidi Pan, Krste Asanović, Robert Cohn, and Chi-Keung Luk, "Controlling Program Execution through Binary Instrumentation", Workshop on Binary Instrumentation and Applications (WBIA-2005), at 14th International Conference on Parallel Architectures and Compilation Techniques (PACT-14), St. Louis, MO, September 2005. PDF

• Seongmoo Heo and Krste Asanović, "Replacing Global Wires with an On-Chip Network: A Power Analysis", International Symposium on Low Power Electronics and Design (ISLPED'05), San Diego, CA, August 2005. PDF

• Jessica H. Tseng and Krste Asanović, "A Speculative Control Scheme for an Energy-Efficient Banked Register File", IEEE Transactions on Computers, 54(6):741-751, June 2005. PDF

• Michael Zhang and Krste Asanović, "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled CMPs", 32nd International Symposium on Computer Architecture (ISCA-32), Madison, WI, June 2005. PDF

• Kenneth C. Barr, Heidi Pan, Michael Zhang, and Krste Asanović, "Accelerating Multiprocessor Simulation with a Memory Timestamp Record", IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005), Austin, TX, March 2005. PDF

• C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, "Unbounded Transactional Memory", 11th International Symposium on High Performance Computer Architecture (HPCA-11), San Francisco, CA, February 2005. PDF
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2005".

• Jared Casper, Ronny Krashinsky, Christopher Batten, and Krste Asanović, "A Parameterizable FPGA Prototype of a Vector-Thread Processor", 1st Workshop on Architecture Research using FPGA Platforms (WARFP-2005), at 11th International Symposium on High Performance Computer Architecture (HPCA-11), San Francisco, CA, February 2005. PDF

• Theses Supervised:
  • Elizabeth A. Basha, "Fast Fourier Transform on a 3D FPGA"
    S.M. Thesis, Massachusetts Institute of Technology, September 2005. PDF
  • Vimal Bhalodia, "SCALE DRAM Subsystem Power Analysis"
    M.Eng. Thesis, Massachusetts Institute of Technology, September 2005. PDF
  • Steven Gerding, "The Extreme Benchmark Suite: Measuring High-Performance Embedded Systems"
    S.M. Thesis, Massachusetts Institute of Technology, September 2005. PDF
  • Rose F. Liu, "AXCIS: Rapid Processor Architectural Exploration using Canonical Instruction Segments"
    M.Eng. Thesis, Massachusetts Institute of Technology, September 2005. PDF

2004

• Christopher Batten, Ronny Krashinsky, Steven Gerding, and Krste Asanović, "Cache Refill/Access Decoupling for Vector Machines", 37th International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004. PDF

• Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding, Brian Pharris, Jared Casper, and Krste Asanović, "The Vector-Thread Architecture", IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences, November/December 2004. PDF
  

• Seongmoo Heo and Krste Asanović, "Power-Optimal Pipelining in Deep Submicron Technology", International Symposium on Low Power Electronics and Design (ISLPED'04), Newport Beach, CA, August 2004. PDF

• Seongmoo Heo and Krste Asanović, "Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage Reduction", Technical Report MIT-LCS-TR-957, Laboratory for Computer Science, Massachusetts Institute of Technology, July 2004. PDF

• Rodric M. Rabbah, Ian Bratt, Krste Asanović, and Anant Agarwal, "Versatility and VersaBench: A New Metric and a Benchmark Suite for Flexible Architectures", Technical Memo, MIT-LCS-TM-646, Laboratory for Computer Science, Massachusetts Institute of Technology, June 2004. PDF

• Ronny Krashinsky, Christopher Batten, Mark Hampton, Steven Gerding, Brian Pharris, Jared Casper, and Krste Asanović, "The Vector-Thread Architecture", 31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004. PDF
  Selected as one of IEEE Micro's "Top Picks from Computer Architecture Conferences, 2004".

• Theses Supervised:
  • Emmett Witchel, "Mondriaan Memory Protection"
    Ph.D. Thesis, Massachusetts Institute of Technology, February 2004. PDF
    Received Honorable Mention, ACM Distinguished Dissertation Awards, 2004.
    Winner, George M. Sprowls Award for best Ph.D. thesis in Computer Science, MIT, 2004.

  • Brian Pharris, "The SCALE DRAM Subsystem"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2004. PDF
  • Sean Lie, "Hardware Support for Unbounded Transactional Memory"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2004. PDF
  • Kelly Koskelin, "EProf: An Energy Profiler for the iPAQ"
    M.Eng. Thesis, Massachusetts Institute of Technology, February 2004. PDF
  • Aaron Mihalik, "VISTA: A Visualization Tool for Computer Architects"
    M.Eng. Thesis, Massachusetts Institute of Technology, February 2004, PDF

2003

• Seongmoo Heo, Kenneth C. Barr, and Krste Asanović, "Reducing Power Density through Activity Migration", International Symposium on Low Power Electronics and Design (ISLPED'03), Seoul, Korea, August 2003. PDF

• Jessica H. Tseng and Krste Asanović, "Banked Multiported Register Files for High-Frequency Superscalar Microprocessors", 30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003. PDF

• Emmett Witchel and Krste Asanović, "Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection", Ninth Workshop on Hot Topics in Operating Systems (HotOS-IX), Lihue, HI, May 2003. PDF

• Kenneth C. Barr and Krste Asanović, "Energy Aware Lossless Data Compression", First International Conference on Mobile Systems, Applications, and Services (MobiSys-2003) , San Francisco, CA, May 2003. PDF
  Winner, Best Paper Award, MobiSys 2003.

• Theses Supervised:
  • Tina Cheng, "Sieve: An XML-Based Structural Verilog Rules Check Tool"
    M.Eng. Thesis, Massachusetts Institute of Technology, August 2003. PDF
  • Regina Sam, "ZOOM: A Performance-Energy Cache Simulator"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2003. PDF
  • Sheetal Jain, "Low-Power Single-Precision IEEE Floating-Point Unit"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2003. PDF
  • Elina Kamenetskaya, "Video over IP: An Example Reconfigurable Computing Application for a Handheld Device"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2003. PDF

2002

• Krste Asanović, "Programmable Neurocomputing", in The Handbook of Brain Theory and Neural Networks: Second Edition, M. A. Arbib (Ed.), MIT Press, ISBN 0-262-01197-2, November 2002. PDF

• Emmett Witchel, Josh Cates, and Krste Asanović, "Mondrian Memory Protection", Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X) , San Jose, CA, October 2002. PDF

• Michael Zhang and Krste Asanović, "Miss Tags for Fine-Grain CAM-Tag Cache Resizing", International Symposium on Low Power Electronics and Design (ISLPED'02), Monterey, CA, August 2002. PDF

• Seongmoo Heo and Krste Asanović, "Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction", VLSI Circuits Symposium, Honolulu, HI, June 2002. PDF

• Krste Asanović, John Hennessy, David A. Patterson, "Vector Processors", Appendix G in Computer Architecture: A Quantitative Approach, Third Edition, Morgan Kaufman, ISBN 1-55860-596-7, May 2002. PDF

• Krste Asanović, Mark Hampton, Ronny Krashinsky, Emmett Witchel, "Energy-Exposed Instruction Sets", in Power Aware Computing, Robert Graybill and Rami Melhem (Eds.), Kluwer Academic/Plenum Publishers, ISBN 0-306-46786-0, May 2002. PDF

• Seongmoo Heo, Kenneth C. Barr, Mark Hampton, and Krste Asanović, "Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines", 29th International Symposium on Computer Architecture (ISCA-29), Anchorage, AK, May 2002. PDF

• Albert Ma and Krste Asanović, "A Double-Pulsed Set-Conditional-Reset Flip-Flop", Technical Report MIT-LCS-TR-844, Laboratory for Computer Science, Massachusetts Institute of Technology, May 2002. PDF

• Theses Supervised:
  • Kenneth C. Barr, "Energy Aware Lossless Data Compression"
    S.M. Thesis, Massachusetts Institute of Technology, September 2002. PDF
  • Heidi Pan, "High-Performance Variable-Length Instruction Encodings"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2002. PDF
    Winner, Charles and Jennifer Johnson Award for best M.Eng. thesis in computer science, MIT, 2002.

2001

• Krste Asanović, "Vector Computing", in The Computer Engineering Handbook, Edited by Vojin G. Oklobdžija, CRC Press, ISBN 0849308852, December 2001.

• Emmett Witchel, Sam Larsen, C. Scott Ananian, and Krste Asanović, "Direct Addressed Caches for Reduced Power Consumption", 34th International Symposium on Microarchitecture (MICRO-34), Austin, TX, December 2001. PDF

• Heidi Pan and Krste Asanović, "Heads and Tails: A Variable-Length Instruction Format Supporting Parallel Fetch and Decode", International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), Atlanta, GA, November 2001. PDF

• Michael Sung, Ronny Krashinsky, and Krste Asanović, "Multithreading Decoupled Architectures for Complexity-Effective General Purpose Computing", Workshop on Memory Access Decoupled Architectures (MEDEA'01), at International Conference on Parallel Architectures and Compilation Techniques (PACT'01), Barcelona, Spain, September 2001. PDF

• Emmett Witchel and Krste Asanović, "The Span Cache: Software Controlled Tag Checks and Cache Line Size", Workshop on Complexity-Effective Design, at 28th International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001. PDF

• Albert Ma, Michael Zhang, and Krste Asanović, "Way Memoization to Reduce Fetch Energy in Instruction Caches", Workshop on Complexity-Effective Design, at 28th International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001. PDF

• Seongmoo Heo and Krste Asanović, "Load-Sensitive Flip-Flop Characterization", IEEE Workshop on VLSI, Orlando, FL, April 2001. PDF

• Seongmoo Heo, Ronny Krashinsky, and Krste Asanović, "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy", 19th Conference on Advanced Research in VLSI (ARVLSI 2001), Salt Lake City, UT, March 2001. PDF

• Theses Supervised:
  • Mark Hampton, "Exposing Datapath Elements to Reduce Microprocessor Energy Consumption"
    S.M. Thesis, Massachusetts Institute of Technology, June 2001. PDF
  • Ronny Krashinsky, "Microprocessor Energy Characterization and Optimization through Fast, Accurate, and Flexible Simulation"
    S.M. Thesis, Massachusetts Institute of Technology, May 2001. PDF

2000

• Michael Zhang and Krste Asanović, "Highly-Associative Caches for Low-Power Processors", Kool Chips Workshop, at 33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000. PDF

• Luis Villa, Michael Zhang, and Krste Asanović, "Dynamic Zero Compression for Cache Energy Reduction", 33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000. PDF

• Jessica H. Tseng and Krste Asanović, "Energy-Efficient Register Access", SBCCI2000, XIII Symposium on Integrated Circuits and System Design, Manaus, Amazonas, Brazil, September 2000. PDF

• Ronny Krashinsky, Seongmoo Heo, Michael Zhang, and Krste Asanović, "SyCHOSys: Compiled Energy-Performance Cycle Simulation", Workshop on Complexity-Effective Design, at 27th International Symposium on Computer Architecture (ISCA-27), June 2000. PDF

• Krste Asanović, "Energy-Exposed Instruction Set Architectures", Work In Progress Session, Sixth International Symposium on High Performance Computer Architecture (HPCA-6), Toulouse, France, January 2000. Published in IEEE TCCA newsletter, June 2000. PDF

• Theses Supervised:
  • Seongmoo Heo, "A Low-power 32-bit Datapath Design"
    S.M. Thesis, Massachusetts Institute of Technology, August 2000. PDF
  • Gong Ke Shen, "A Procedural Layout Library in Java"
    M.Eng. Thesis, Massachusetts Institute of Technology, May 2000. PDF

1999

• Theses Supervised:
  • Jessica H. Tseng, "Energy-Efficient Register File Design"
    S.M. Thesis, Massachusetts Institute of Technology, December 1999. PDF
  • Mukaya Panich, "Reducing Instruction Cache Energy Using Gated Wordlines"
    M.Eng. Thesis, Massachusetts Institute of Technology, August 1999. PDF)

1998

• Krste Asanović, James Beck, David Johnson, John Wawrzynek, Brian E. D. Kingsbury, and Nelson Morgan, "Training Neural Networks with Spert-II". Chapter 11 in Parallel Architectures for Artificial Neural Networks: Paradigms and Implementations, N. Sundararajan and P. Saratchandran (Eds.), IEEE Computer Society Press, ISBN 0-8186-8399-6, November 1998, pp 345-364. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "The PHiPAC v1.0 Matrix-Multiply Distribution". Technical Report TR-98-035, International Computer Science Institute, Berkeley, October 1998. Also listed as UCB CS technical report UCB/CSD-98-1020. PDF

• Krste Asanović, "A vector processing system with multi-operation run-time reconfigurable pipelines", US Patent 5,805,875, issued September 1998. PDF

• Krste Asanović, "Vector Microprocessors", Ph.D. Thesis, University of California, Berkeley, May 1998. The thesis is also available as Technical Report UCB/CSD-98-1014, Computer Science Division, University of California, Berkeley.

1997

• Philipp Faerber and Krste Asanović, "Parallel neural network training on Multi-Spert", IEEE 3rd International Conference on Algorithms and Architectures for Parallel Processing, Special session on Parallel Algorithms and Architectures for Neural Processing, Melbourne, Australia, December 1997. Postscript, PDF.

• David A. Patterson, Krste Asanović, Aaron Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, and Katherine Yelick. "Intelligent RAM (IRAM): the industrial setting, applications, and architecture", International Conference on Computer Design (ICCD'97), Austin, Texas, 10-12 October 1997. PDF

• Christoforos Kozyrakis, Stylianos Perissakis, David A. Patterson, Thomas Anderson, Krste Asanović, Neal Cardwell, Richard Fromm, Jason Golbus, Ben Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, and Kathy Yelick, "Scalable processors in the billion-transistor era: IRAM", IEEE Computer, September 1997. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology", 11th ACM International Conference on Supercomputing (ICS'97), July 1997. PDF

• Krste Asanović, "A fast Kohonen net implementation for Spert-II", IWANN''97, Lanzarote, Canary Islands, Spain, June 1997. PDF

• Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, "Using PHiPAC to speed error back-propagation learning", International Conference on Acoustics, Speech, and Signal Processing (ICASSP'97), Munich, Germany, April 1997, Volume 5, pp4153-4157. PDF

1996

• Krste Asanović and James Beck, "T0 Engineering Data", Technical Report TR-96-057, International Computer Science Institute, Berkeley, December 1996. Also listed as UCB CS technical report UCB/CSD-97-931. PDF

• Krste Asanović and David Johnson, "Torrent Architecture Manual", Technical Report TR-96-056, International Computer Science Institute, Berkeley, December 1996. Also listed as UCB CS technical report UCB/CSD-97-930. PDF

• Krste Asanović, Brian Kingsbury, Bertrand Irissou, James Beck, and John Wawrzynek "T0: A single-chip vector microprocessor with reconfigurable pipelines", In Proceedings 22nd European Solid-State Circuits Conference (ESSCIRC'96), Editor: H. Grunbacher, Editions Frontieres, September, 1996, pp344-347. Postscript, PDF

• Jeff Bilmes, Krste Asanović, Jim Demmel, Dominic Lam, and Chee-Whye Chin "Optimizing Matrix Multiply using PHiPAC: a Portable, High-Performance, ANSI C Coding Methodology", LAPACK Working Note 111, Technical Report UT-CS-96-326, University of Tennessee, Knoxville, August 1996. PDF

• John Wawrzynek, Krste Asanović, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan, "Spert-II: A vector microprocessor system", IEEE Computer, 29(3):79-86, March 1996. PDF.

1995

• Krste Asanović, James Beck, Bertrand Irissou, Brian Kingsbury, Nelson Morgan, and John Wawrzynek, "The T0 vector microprocessor", Proceedings HOT Chips VII, Stanford, CA, August 1995. PDF

1994

• Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, and John Wawrzynek, "A supercomputer for neural computation", Proceedings of the International Conference on Neural Networks, volume 1, pages 5-9, June 1994. PDF

1993

• Krste Asanović, Nelson Morgan, John Wawrzynek, "Using Simulations of Reduced Precision Arithmetic to Design a Neuro-Microprocessor", Journal of VLSI Signal Processing, 6:33-44, June 1993.

• John Wawrzynek, Krste Asanović, Nelson Morgan, "The Design of a Neuro-Microprocessor", IEEE Transactions on Neural Networks, 4(3), May 1993. PDF

• Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan, and John Wawrzynek, "Development of a Connectionist Network Supercomputer", Proceedings of the Third International Conference on Microelectronics for Neural Networks, pp 253-262, April 1993. A version is available as an ICSI Technical Report TR-93-021.

1992

• Denis B. Howe and Krste Asanović, "SPACE: Symbolic Processing in Associative Computing Elements", VLSI for Neural Networks and Artificial Intelligence, Editors: Jose G. Delgado-Frias and William R. Moore, Plenum Press, 1994, pp 243-252. From Proceedings 3rd International Workshop on VLSI for Artificial Intelligence and Neural Networks, September 1992. HTML, Postscript, PDF

• Krste Asanović, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, and John Wawrzynek, "SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations", Application Specific Array Processors Conference (ASAP'92), Berkeley, USA, August 1992, pp178-190. A version of this paper is available as ICSI Technical Report TR-91-072.

• Krste Asanović, Klaus Erik Schauser, David A. Patterson, and Edward H. Frank, "Evaluation of a stall cache: An efficient restricted on-chip instruction cache", Proceedings 25th Hawaii International Conference on System Sciences pp 405-415, January 1992. PDF
  An expanded version of this paper is available as UCB Technical Report UCB/CSD 91/641.

1991

• Krste Asanović and Nelson Morgan, "Experimental Determination of Precision Requirements for Back-Propagation Training of Artificial Neural Networks", Proceedings 2nd International Conference on Microelectronics for Neural Networks, October 1991, Munich. A version of this paper is available as ICSI Technical Report TR-91-036.

1990

• Krste Asanović, Brian Kingsbury, Nelson Morgan, and John Wawrzynek, "HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training", Proceedings IFIP Workshop on Silicon Architectures for Neural Nets, pp 217-232, November 1990, St Paul de Vence, France. A version of this paper is available as ICSI Technical Report TR-91-035.

1988

• Krste Asanović and James R. Chapman, "Spoken Natural Language Understanding as a Parallel Application", Proceedings CONPAR88, volume B, BCS Parallel Processing Specialist Group, September 1988. Paper (text only) PDF.