Research

 

My current research is the hardware implementation of Maskless Lithography.

        We investigate hardware implementation of the data path compression algorithms in mask-less lithography. As the physical size of semiconductor devices become smaller, the traditional optical lithography techniques become impractical due to the physical constraints of the mask material. To solve this problem, direct-write maskless lithography approaches are under consideration.

        To achieve acceptable throughput with mask-less lithography, we have to deal with the data rates of 10Tb/s, and as such, data compression techniques need to be applied. Specifically, the layout data is compressed beforehand, sent to the writer, and decompressed inside the writer to generate actual pixel values.

 

        Vito Dai has developed a lossless compression scheme, called C4, for layout that outperforms all other lossless compression techniques such as LZ and its variations. In this project, we consider hardware implementation aspects of the decoder for the C4 algorithm and its variations. Our approach is to first develop the hardware block diagram model of decoder, and then test the performance on FPGA board. The final goal is to build a decoder chip for C4.

 

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