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Research Abstract Energy-efficiency has displaced performance as the primary design constraint in optimizing digital integrated circuits. The task of estimating tradeoffs between power (energy) and performance (delay) for each choice of design parameter at each level of design hierarchy is inherently complex and time consuming as it spans a multi-dimensional search space across multiple levels of design abstraction. In this research we explore the use of sensitivity information to systematically and automatically optimize circuits in a synthesis-based design environment. We begin by quantifying the difference between synthesized and custom optimized circuits, and then develop models to capture interface constraints and sensitivities to tuning variables. The models are used to evaluate design tradeoffs in the energy-delay space at the micro-architecture and circuit levels. The models enable systematic traversal of the tradeoff space across levels of design abstraction in the context of circuit-level constraints such as gate size, supply voltage, and wire capacitance. We demonstrate our optimization methods by synthesizing and optimizing Verilog models of hierarchical data-paths such as integer execution units, digital FIR filters, and Viterbi decoders within a synthesis-based design environment. Energy-efficiency gains are exploited to evaluate flexible datapath architectures (e.g. digital FIR filters and Viterbi decoders) for baseband receivers that support multi-standard wireless communication. |