Eric Chin

Eric Chin
Graduate Student Researcher
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley

Biography

Eric Chin is a Ph.D. Candidate in the department of EECS at UC Berkeley. He received his Bachelors of Science degree from Cornell University in 2005. Eric has held multiple internship positions at Sandcraft, Inc., Intel Corporation, Advanced Micro Devices, and Cadence Design Systems. His research interests include robust integrated circuit design, CAD synthesis flows, optical proximity correction, process variations, and design for manufacturing solutions. Eric is being advised by Professor Andrew Neureuther. He is also an IBM/SRC Fellow.

Publications

E. Chin, J. Holwill, and A. Neureuther, "Prediction of Interconnect Delay Variations using Pattern Matching." SPIE Advanced Lithography, Proceedings of SPIE Vol 6521(21), San Jose, 2007.
A. Neureuther, W. Poppe, J. Holwill, E. Chin, L.T.-N Wang, J.-S. Yang, M. Miller, D. Ceperley, C. Clifford, K. Kikuchi, J. Choi, D. Dornfeld, P. Friedberg, C. Spanos, J. Hoang , J. Chang, J. Hsu, D. Graves, A. Wu , and M. Lieberman. "Collaborative Platform, Tool-Kit, and Physical Models for DfM." SPIE Advanced Lithography, Proceedings of SPIE Vol 6521(21), San Jose, 2007.