|
|
|
Nano-Electro-Mechanical Integrated Circuits
F. Chen, H. Kam, D. Markovic, T.-J. King Liu, V. Stojanovic, and E. Alon, Integrated Circuit Design with NEM Relays, IEEE International Conference on Computer-Aided Design, Nov. 2008.
On-Die Power Supply Integrity
E. Alon and M. Horowitz,Integrated Regulation for Energy-Efficient Digital Circuits, IEEE Journal of Solid-State Circuits, Aug. 2008.
E. Alon and M. Horowitz, Integrated Regulation for Energy-Efficient Digital Circuits, IEEE Custom Integrated Circuits Conference, Sept. 2007.
E. Alon, Measurement and Regulation of On-Chip Power Supply Noise, Ph.D. Thesis, Stanford University, Dec. 2006.
E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops, IEEE Journal of Solid-State Circuits, Feb. 2006.
S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, E. Alon, and M. Horowitz, The Implementation of a 2-core, Multi-Threaded Itanium Family Processor, IEEE Journal of Solid-State Circuits, Jan. 2006.
V. Abramzon, E. Alon, B. Nezamfar, and M. Horowitz, Scalable Circuits for Supply Noise Measurement, IEEE European Solid-State Circuits Conference, Sept. 2005.
E. Alon, V. Stojanovic, and M. Horowitz, Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise, IEEE Journal of Solid-State Circuits, April 2005.
E. Alon, V. Stojanovic, and M. Horowitz, Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise, IEEE Symposium on VLSI Circuits, June 2004.
High-Speed Electrical Links
C. Werner, C. Hoyer, A. Ho, M. Jeeradit, F. Chen, B. Garlepp, W. Stonecypher, S. Li, A. Bansal, A. Agarwal, E. Alon, V. Stojanovic, and J. Zerbe, Modeling, Simulation, and Design of a Multi-Mode 2-10 Gb/sec Fully Adaptive Serial Link System, IEEE Custom Integrated Circuits Conference, Sept. 2005.
V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, G. Tsang, E. Alon, R. Kollipara, C. Werner, J. Zerbe, and M. A. Horowitz, Autonomous Dual-mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery, IEEE Journal of Solid-State Circuits, April 2005.
K. Chang, S. Pamarti, K. Kaviani, E. Alon, X. Shi, T. Shin, J. Shen, G. Yip, C. Madden, R. Schmitt, C. Yuan, F. Assaderaghi, and M. Horowitz, Clocking and Circuit Design for a Parallel I/O on a First Generation CELL Processor, IEEE International Solid-State Circuits Conference, Feb. 2005.
V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, and M. A. Horowitz, Adaptive Equalization and Data Recovery in a Dual-Mode (PAM2/4) Serial Link Transceiver, IEEE Symposium on VLSI Circuits, June 2004.
A. Ho, V. Stojanovic, F. Chen, C. Werner, G. Tsang, E. Alon, R. Kollipara, J. Zerbe, and M. A. Horowitz, Common-mode Backchannel Signaling System for Differential High-speed Links, IEEE Symposium on VLSI Circuits, June 2004.
Multi-Mode Fiber Optical Communication
Miscellaneous
M. Horowitz, D. Stark, and E. Alon, Digital Circuit Design Trends, IEEE Journal of Solid-State Circuits, Apr. 2008.
M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, Scaling, Power, and the Future of CMOS, IEEE International Electron Devices Meeting, Dec. 2005.
Smart Memories
K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, and M. Horowitz, Architecture and Circuit Techniques for a 1.1GHz 16Kb Reconfigurable Memory in 0.18um CMOS, IEEE Journal of Solid-State Circuits, Jan. 2005.
K. Mai, R. Ho, E. Alon, D. Liu, Y. Kim, D. Patil, and M. Horowitz, Architecture and Circuit Techniques for a Reconfigurable Memory in 0.18um CMOS, IEEE International Solid-State Circuits Conference, Feb. 2004.
|
|
|
|
