Chung-Wei Lin
林忠緯

E-mail: cwlin at eecs.berkeley.edu

EDUCATION [More]
2009--Present: Ph.D. Student, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
2005--2007: M.S., Graduate Institute of Electronics Engineering, National Taiwan University
2001--2005: B.S., Department of Computer Science and Information Engineering, National Taiwan University

PUBLICATIONS
Journal Papers:
  1. C.-W. Lin, Q. Zhu, and A. Sangiovanni-Vincentelli, "Security-aware modeling and efficient mapping for CAN-based real-time distributed automotive systems," accepted and to appear in IEEE Embedded Systems Letters (ESL), 2014.
  2. C.-W. Lin, L. Rao, J. D'Ambrosio, and A. Sangiovanni-Vincentelli, "Electrical architecture optimization and selection---cost minimization via wire routing and wire sizing," in SAE International Journal of Passenger Cars---Electronic and Electrical Systems, vol. 7, no. 2, pp. 502--509, Aug. 2014.
  3. C.-W. Lin and A. Sangiovanni-Vincentelli, "Cyber-security for the Controller Area Network (CAN) communication protocol," in ASE Science Journal, vol. 1, no. 2, pp. 80--92, Dec. 2012.
  4. C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, "An efficient pre-assignment routing algorithm for flip-chip designs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 6, pp. 878--889, Jun. 2012.
  5. C.-W. Lin, S.-L. Huang, K.-C. Hsu, M.-X. Lee, and Y.-W. Chang, "Multi-layer obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 2007--2016, Nov. 2008.
  6. C.-H. Liu, H.-Y. Liu, C.-W. Lin, S.-J. Chou, Y.-W. Chang, S.-Y. Kuo, S.-Y. Yuan, and Y.-W. Chen, "An efficient graph-based algorithm for ESD current path analysis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 8, pp. 1363--1375, Aug. 2008.
  7. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, "Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 4, pp. 643--653, Apr. 2008.
Major Conference Papers:
  1. C.-W. Lin, Q. Zhu, and A. Sangiovanni-Vincentelli, "Security-aware mapping for TDMA-based real-time distributed systems," accepted and to appear in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2014.
  2. C.-W. Lin, T.-H. Hsu, X.-W. Shih, and Y.-W. Chang, "Buffered clock tree synthesis considering self-heating effects," in Proceedings of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 111--116, La Jolla, CA, Aug. 2014. (Acceptance Rate = 34%)
  3. C.-W. Lin, L. Rao, P. Giusto, J. D'Ambrosio, and A. Sangiovanni-Vincentelli, "An efficient wire routing and wire sizing algorithm for weight minimization of automotive systems," in Proceedings of ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jun. 2014. (Acceptance Rate = 22%)
  4. C.-W. Lin, L. Rao, J. D'Ambrosio, and A. Sangiovanni-Vincentelli, "Electrical architecture optimization and selection---cost minimization via wire routing and wire sizing," in SAE World Congress & Exhibition, Detroit, MI, Apr. 2014. (Selected to SAE Journal)
  5. C.-W. Lin, Q. Zhu, C. Phung, and A. Sangiovanni-Vincentelli, "Security-aware mapping for CAN-based real-time distributed automotive systems," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 115--121, San Jose, CA, Nov. 2013. (Acceptance Rate = 26%)
  6. C.-W. Lin, M. Di Natale, H. Zeng, L. T. X. Phan, and A. Sangiovanni-Vincentelli, "Timing analysis of process graphs with finite communication buffers," in Proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 227--236, Philadelphia, PA, Apr. 2013. (Acceptance Rate = 29%)
  7. S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, "Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling," in Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 77--84, Stateline, NV, Mar. 2013. (Acceptance Rate = 31%; Best Paper Nominee)
  8. C.-W. Lin and A. Sangiovanni-Vincentelli, "Cyber-security for the Controller Area Network (CAN) communication protocol," in Proceedings of ASE International Conference on Cyber Security (CyberSecurity), pp. 344--350, Washington, DC, Dec. 2012. (Top 3% Paper; Selected to ASE Journal)
  9. S.-L. Huang, C.-W. Lin, and Y.-W. Chang, "Efficient provably good OPC modeling and its applications to interconnect optimization," in Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 336--341, Amsterdam, Netherlands, Oct. 2010. (Acceptance Rate = 30%; Best Paper Award)
  10. P.-W. Lee, C.-W. Lin, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, "An efficient pre-assignment routing algorithm for flip-chip designs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 239--244, San Jose, CA, Nov. 2009. (Acceptance Rate = 26%)
  11. C.-W. Lin, S.-L. Huang, K.-C. Hsu, M.-X. Lee, and Y.-W. Chang, "Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 380--385, San Jose, CA, Nov. 2007. (Acceptance Rate = 27%)
  12. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, "Efficient obstacle-avoiding rectilinear Steiner tree construction," in Proceedings of ACM International Symposium on Physical Design (ISPD), pp. 127--134, Austin, TX, Mar. 2007. (Acceptance Rate = 34%; Best Paper Nominee)
  13. C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang, and Y.-W. Chang, "Recent research and emerging challenges in physical design for manufacturability/reliability," in Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 238--243, Yokohama, Japan, Jan. 2007. (Invited Paper)
  14. H.-Y. Liu, C.-W. Lin, S.-J. Chou, W.-T. Tu, C.-H. Liu, Y.-W. Chang, and S.-Y. Kuo, "Current path analysis for electrostatic discharge protection," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 510--515, San Jose, CA, Nov. 2006. (Acceptance Rate = 24%)
  15. C.-W. Lin, Y.-C. Chen, and A.-C. Pang, "A new resource allocation scheme for IEEE 802.16-based networks," in Proceedings of IEEE VTS Asia Pacific Wireless Communications Symposium (APWCS), Daejeon, Korea, Aug. 2006.
Other Conference Papers:
  1. C.-W. Lin, M. Di Natale, H. Zeng, and A. Sangiovanni-Vincentelli, "Performance analysis of synchronous models implementations on loosely time-triggered architectures," in Work-in-Progress Session of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Chicago, IL, Apr. 2011.
  2. P.-W. Lee, C.-W. Lin, and Y.-W. Chang, "Fast pre-assignment flip-chip routing," in VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009. (Best Paper Nominee; Selection was cancelled due to typhoon Morakot)
Patent:
  1. C.-F. Chang, C.-F. Shen, H.-S. Chiu, I.-J. Lin, T.-C. Hsu, Y.-W. Chang, C.-W. Lin, and P.-W. Lee, "Routing method for flip chip package and apparatus using the same metal layer," US Patent 8,578,317, Oct. 2010.
Thesis:
  1. C.-W. Lin, "Efficient obstacle-avoiding rectilinear Steiner tree construction," Master's Thesis, National Taiwan University, Jun. 2007.

COURSES [More]
2009--Present (EECS, UC Berkeley): GPA = 4.00 / 4.00 (A+ or A), #Credits = 27, Rank = N/A
2005--2007 (GIEE, NTU): GPA = 4.00 / 4.00 (93.14 in 100-point scale), #Credits = 22+12, Rank = 3 (among 132 students)
2001--2005 (CSIE, NTU): GPA = 4.00 / 4.00 (92.02 in 100-point scale), #Credits = 169, Rank = 2 (among 108 students)

SELECTED HONORS
EECS Department Fellowship, EECS, UC Berkeley, 2009.08
The Best M.S. Thesis Award, GIEE, NTU, 2007.12
The 1st Prize, Youth Thesis Award, Chinese Institute of Electrical Engineering, 2007.12
The 1st Prize, IC/CAD Contest, Ministry of Education, Taiwan, 2007.07
Member of Phi-Tau-Phi Scholastic Honor Society (Top 3% Graduate Students), 2007.06
Two-Time EDA Scholarship, SpringSoft Education Foundation, 2007.07, 2006.07
Incentia Scholarship (Rank 1st in Program Entrance Competition of EDA Group), 2005.09
Two-Time Champion, Tennis Team Competition, National College Games, 2006.04, 2004.03
Member of Phi-Tau-Phi Scholastic Honor Society (Top 1% Undergraduate Students), 2005.06
Six-Time Presidential Award (Top 5% Students), NTU, 2005.04, 2004.10, 2004.04, 2003.04, 2002.10, 2002.04

EXPERIENCES
Two-Time Graduate Student Instructor, Discrete Mathematics and Probability Theory, UC Berkeley, 2014.01--2014.05, 2013.01--2013.05
Three-Time Summer Intern, General Motors, 2013.05--2013.08, 2012.05--2012.08, 2011.05--2011.08
Research Assistant (Joint Project), Synopsys Taiwan, 2009.02--2009.07
Research Assistant, NTU, 2009.02--2009.07
Military Instructor in Information System (Second Lieutenant), R.O.C. Army, 2007.11--2008.06
Compulsory Military Service, R.O.C. Army, 2007.07--2008.06
Research Assistant (Joint Project), Taiwan Semiconductor Manufacturing Company, 2006.05--2007.06
Teaching Assistant, Nonlinear Programming, NTU, 2007.02--2007.06
Teaching Assistant, Logic Synthesis and Verification, NTU, 2006.09--2007.01

ACTIVITIES
Member of NTU Tennis Team, 2002.09--2007.06
Chairman of NTU EECS College Students Association, 2003.07--2004.06