Cadence Distinguished Professor of Electrical Engineering and Computer Science,

Department of EECS, 573 Cory Hall, University of California, Berkeley, CA, 94720





Place of Birth: Des Moines, Iowa

Marital Status: Married (Wife - Ruth, Children - Jane, James, Michael)

Education: B.S., Electrical Engineering, Iowa State University, Ames, Iowa, 1956 Ph.D., Mathematics, MIT, Cambridge, MA, 1961

PhD Thesis: On the Asymptotic Behavior of the Number of Trials Necessary to Complete a Set with Random Selection.

Advisor: Professor Norman Levinson


Professional Experience:

(1999-present)      Cadence Distinguished Professor of EECS

(1997-1999)         Edgar L. and Harold H. Buttner Chair of Electrical Engineering

(1987-present)      Professor EECS, Berkeley

 (1992-93)             Visiting Professor, Electrical Engineering, T.U. Delft, The Netherlands

(1961-1987)         Research Staff Member, IBM Thomas J. Watson Research Center, Yorktown Heights, NY

(1985-1986)         Visiting McKay Professor EECS Dept., U. C. Berkeley

(1984-1987)         Second-Level Manager, Mathematical Algorithms (Logic Design, General Mathematics, Mathematical Programming, Parallel Computing)

(1981-1984)         Second-Level Manager, Logic Design, Differential Equations, Computer Algebra

(1981-1985)         Manager, Logic Design

(1975-1976)         Visiting Professor Electrical Engineering, Imperial College, London

(1971-1972)         Assistant Director, Mathematical Sciences Department IBM Research

(1966-1967)         Visiting Associate Professor Electrical Engineering, MIT

(1963-1981)         Manager, Differential Equations and Numerical Analysis

(1957-1961)         Massachusetts Institute of Technology, Cambridge, MA, Research Assistant in Artificial Intelligence – Developed first of LISP compiler.

(1957)                    Second Lieutenant, U.S. Army Corps of Engineers

(1956-1957)         Remington Rand Univac, St. Paul, Minnesota, Electrical Engineer



American Association for the Advancement of Science


IEEE Circuits and Systems Administrative Committee 1979-1982. 

NSF Mathematics Advisory Committee 1970-1973.

IEEE Committees - CANDE, Large-Scale Systems, Nonlinear Systems


Awards and Honors:

Fellow of IEEE - 1980

Fellow of AAAS - 1972

National Academy of Engineering - 1993

IBM Outstanding Innovation Awards:

1970 - for the sparse tableau method

1981 - for methods for cascode logic synthesis and fast Boolean function manipulation.

IBM Invention Awards:

first plateau - 1976

second plateau - 1987

Best Paper Awards:

The IEEE Circuits and Systems Guilleman-Cauer – 1971 (sparse tableau method)

The IEEE Darlington Award  - 1987

HICSS- 1990

Sixth Inter. Conf. on VLSI Design, Bombay - 1993

Eighth Inter. Conf. on VLSI Design, New Delhi - 1995

Design and Test Conference (DATE) - 2002

Medals and Achievement Awards:

The IEEE Circuits and Systems Technical Achievement Award - 1992

Iowa State University PACE (alumni) Award - 1993

CAS Golden Jubilee Medal - 2000

IEEE Millennium Medal - 2000

The Iowa State University Marston Medal – 2002



Associate Editor, IEEE Transactions on CAD of Circuits and Systems - 1987-1992

Editor, Formal Methods in System Design - 1991-1997



10 books -

“Modern Network Analysis - An Introduction”,

“Computer Aided Design: Sensitivity and Optimization”,

“Logic Minimization Algorithms for VSLI Synthesis”,

“Integrating Functional and Temporal Domains in Logic Design”,

“Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis”,

“Logic Synthesis for Field-Programmable Gate Arrays”,

“Synthesis of Finite State Machines: Functional Optimization”,

“Synthesis of Finite State Machines: Logic Optimization”,

“Cross-talk Immune VLSI Design Using Regular Layout Fabrics”,

“Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design”


Over 450 technical publications in the areas of Nonlinear Networks, Stability Theory, Numerical Methods for Differential Equations, Sparse Matrices, Simulation of Electrical Circuits, Optimization Methods for Circuit Design, Combinational and Sequential Logic Synthesis for Area/Performance/Testability, and Use of Formal Verification in the Design Process.